Memory cell arrangements and method of operating a memory cell

Abstract

Memory cell arrangements and methods of operating a memory cell are disclosed, wherein a memory cell arrangement includes a memory cell including: a field-effect transistor including a gate terminal, a first source/drain terminal, and a second source/drain terminal; and a spontaneously-polarizable capacitor connected to the first source/drain terminal of the field-effect transistor, the spontaneously-polarizable capacitor having a first capacitance; and a write modification circuit electrically conductively connected to the second source/drain terminal or to the spontaneously-polarizable capacitor, wherein the write modification circuit includes a write capacitor having a second capacitance and wherein the write modification circuit is configured to selectively provide the second capacitance when the memory cell is written.

Dependencies are inferred from the claim text.