Cross-point array leakage compensation
AssigneeSanDisk Technologies LLC
InventorJuan P. Saenz
Life of this patent
Estimating the term…
Abstract
Technology for a system and method for controlling leakage current in a cross-point array having programmable resistance memory cells. The slope of a trailing edge of a pulse that is applied to a selected memory cell may depend on a wear factor of the selected memory cell. The wear factor may be based on a number of times the selected memory cell has been accessed by writes and/or reads. The memory system may flatten the slope of the trailing edge of the pulse as the selected memory cell experiences more wear.
Claims20
An apparatus comprising:
- a cross-point memory array a plurality of first conductive lines, a plurality of second conductive lines, and magnetoresistive random access memory (MRAM) cells, each MRAM cell connected between one of the first conductive lines and one of the second conductive lines, each MRAM cell having a two-terminal threshold switching selector in series with a magnetic tunnel junction;
- and
- one or more control circuits in communication with the cross-point memory array, the one or more control circuits configured to:
- determine a wear factor for a selected MRAM cell;
- generate a pulse to apply to a selected MRAM cell, wherein a slope of a trailing edge of the pulse depends on the wear factor;
- and
- apply the pulse to the selected MRAM cell.
A method for operating a cross-point memory array having magnetoresistive random access memory (MRAM) cells, each MRAM cell connected between one of a plurality of first conductive lines and one of a plurality of second conductive lines, the method comprising:
- determining a slope for a pulse based on a number of memory accesses performed on a selected MRAM cell, wherein an absolute value of the slope increases with increases in the number of memory accesses;
- generating the pulse having the slope;
- and
- applying the pulse to a first conductive line connected to the selected MRAM cell while applying a select voltage to a second conductive line connected to the selected MRAM cell to turn on a two-terminal threshold switching selector of the selected MRAM cell.
A memory system comprising:
- a cross-point memory array a plurality of first conductive lines, a plurality of second conductive lines, and MRAM cells, each MRAM cell connected between one of the first conductive lines and one of the second conductive lines, each MRAM cell having a two-terminal threshold switching selector in series with a magnetic tunnel junction;
- and
- one or more control circuits in communication with the cross-point memory array, the one or more control circuits configured to:
- track memory accesses performed on a selected MRAM cell connected between a selected first conductive line and a selected second conductive line;
- generate a pulse having a trailing edge having a duration that depends on the memory accesses, the pulse having a peak magnitude greater than a threshold voltage of the threshold switching selector in the selected MRAM cell;
- and
- apply the pulse to the selected first conductive line while applying a select voltage to the selected second conductive line to switch on the threshold switching selector in selected MRAM cell.
Dependencies are inferred from the claim text.