Bit line sense amplifier offset cancellation in memory circuits

A method comprising:

• regulating a first voltage difference between a first bit line (BL) and a second BL at a first instant in a first offset cancellation (OC) interval within an OC period, the first voltage difference being associated with a first threshold mismatch between two or more transistors of a first conductivity type in a first part of a sense amplifier;
• and
• regulating a temporal voltage inequality at a second instant in a second OC interval within the OC period, the temporal voltage inequality being associated with a second threshold mismatch between two or more transistors of a second conductivity type in a second part of the sense amplifier,
• wherein regulating the temporal voltage inequality comprises modifying a control signal that controls the second part.

A system comprising:

• a processor configured to execute a program;
• and
• a memory configured to store the program and comprising a memory circuit comprising:
• a first circuit configured to regulate a first voltage difference between a first bit line (BL) and a second BL at a first instant in a first offset cancellation (OC) interval within an OC period, the first voltage difference being associated with a first threshold mismatch between two or more transistors of a first conductivity type in a first part of a sense amplifier;
• and
• a second circuit configured to regulate a temporal voltage inequality at a second instant in a second OC interval within the OC period, the temporal voltage difference being associated with a second threshold mismatch between two or more transistors of a second conductivity type in a second part of the sense amplifier,
• wherein the second circuit regulating the temporal voltage inequality includes modifying a control signal that controls the second part.