Single ended memory sensing architecture

A semiconductor device, comprising:

• a memory array, including bit cells and a data bit line coupled to the bit cells;
• a data pre-charge current source coupled to the data bit line, the data pre-charge current source being structured to provide a data pre-charge current to the data bit line;
• a dummy bit line;
• a dummy pre-charge current source coupled to the dummy bit line, the dummy pre-charge current source being structured to provide a dummy pre-charge current to the dummy bit line;
• and
• a threshold detector connected to the dummy bit line, the threshold detector being structured to provide a threshold signal a when a potential on the dummy bit line reaches a threshold potential.

A semiconductor device, comprising:

• a memory array, including bit cells and a data bit line connected to one of the bit cells;
• and
• a sense amplifier, including:
• an input inverter stage having a signal input and a signal output, the signal input being coupled to the data bit line;
• a shunt switch having a control node, the shunt switch connecting the signal input to a reference line, the control node being structured to cause the shunt switch to vary an impedance of the shunt switch;
• and
• a feedback connection between the signal output of the input inverter stage and the control node, wherein the feedback connection and the shunt switch provide a positive feedback loop for the input inverter stage.

A method of forming a semiconductor device, comprising:

• forming a memory array in or over a semiconductor substrate, the memory array including bit cells and a data bit line coupled to the bit cells;
• forming a data pre-charge variable current source coupled to the data bit line, the data pre-charge variable current source being structured to provide a first data pre-charge current to the data bit line and to provide a second data pre-charge current to the data bit line that is less than the first data pre-charge current;
• and
• forming a pre-charge controller connected to the data pre-charge variable current source, the pre-charge controller being structured to:
• cause the data pre-charge variable current source to provide the first data pre-charge current to the data bit line;
• and
• subsequently cause the data pre-charge variable current source to provide the second data pre-charge current to the data bit line.