Method of detecting sense margin of memory read operation and related sense margin detecting circuit

A sense margin detecting circuit of memory read operation, comprising:

• a first multiplexer, including:
• a first input end coupled to a bit line voltage;
• a second input end coupled to a reference voltage;
• and
• an output end coupled to a first input end of a sense amplifier for selectively outputting the bit line voltage or the reference voltage to the first input end of the sense amplifier based on a first control signal;
• a second multiplexer, including:
• a first input end coupled to the reference voltage;
• a second input end coupled to the bit line voltage;
• and
• an output end coupled to a second input end of the sense amplifier for selectively outputting the bit line voltage or the reference voltage to the second input end of the sense amplifier based on a second control signal;
• a de-multiplexer, including:
• a first input end coupled to an output end of the sense amplifier for receiving a data signal outputted by the sense amplifier;
• a first output end for selectively outputting the data signal based on a third control signal so as to provide a corresponding first data signal during a first phase;
• and
• a second output end for selectively outputting the data signal based on the third control signal so as to provide a corresponding second data signal during a second phase;
• and
• a logic circuit configured to output a sense margin detecting signal based on the first data signal and the second data signal during a third phase, wherein:
• the first phase is followed by the second phase and the second phase is followed by the third phase;
• or
• the second phase is followed by the first phase and the first phase is followed by the third phase.