Shift register unit, gate driving circuit, and gate driving method

A shift register unit, comprising:

• a sensing control circuit connected to a first sensing control node, a sensing signal input terminal, a random signal input terminal, and a sensing active level supply terminal, and configured to write an active level signal provided by the sensing active level supply terminal to the first sensing control node in response to control of an active level signal provided by the random signal input terminal and an active level signal provided by the sensing signal input terminal;
• a first sensing input circuit connected to the first sensing control node, a clock control signal input terminal, and a first pull-up node, and configured to write an active level signal to the first pull-up node in response to control of an active level signal at the first sensing control node and an active level signal provided by the clock control signal input terminal;
• and
• a first driving output circuit connected to the first pull-up node, a first driving clock signal input terminal, and a first driving signal output terminal, and configured to write a signal provided by the first driving clock signal input terminal to the first driving signal output terminal in response to control of an active level signal at the first pull-up node,
• wherein the sensing control circuit comprises:
• a first control input circuit connected to the sensing active level supply terminal, a sensing control intermediate node, and a first control signal input terminal, and configured to write a signal provided by the sensing active level supply terminal to the sensing control intermediate node in response to control of an active level signal provided by the first control signal input terminal;
• and
• a second control input circuit connected to the sensing control intermediate node, the first sensing control node, and a second control signal input terminal, and configured to write a signal at the sensing control intermediate node to the first sensing control node in response to control of an active level signal provided by the second control signal input terminal;
• and
• one of the first control signal input terminal and the second control signal input terminal is the sensing signal input terminal, and the other is the random signal input terminal.