Buffer circuit, display device and electronic device including the same

A display device, comprising:

• a plurality of pixels;
• a scan driver connected to the plurality of pixels through a plurality of scan lines;
• a data driver connected to the plurality of pixels through a plurality of data lines configured to receive an image data signal and to transmit a corresponding analog voltage;
• a driving controller configured to control operations of the scan driver and the data driver, and to provide a clock signal to the scan driver;
• and
• a buffer circuit configured to compensate for distortion of the clock signal,
• wherein the buffer circuit comprises:
• a pull-up transistor connected between a first voltage source and an output node;
• a pull-down transistor connected between the output node and a second voltage source;
• and
• at least one voltage boosting circuit configured to receive the clock signal, to generage a boosting signal by amplifying an amplitude of the clock signal, and to transmit the boosting signal to a gate electrode of the pull-down transistor.

An electronic device, comprising:

• a processor configured to provide input image data;
• and
• a display device configured to display an image based on the input image data,
• wherein the display device comprises:
• a plurality of pixels;
• a scan driver connected to the plurality of pixels through a plurality of scan lines;
• a data driver connected to the plurality of pixels through a plurality of data lines configured to receive an image data signal and to transmit a corresponding analog voltage;
• a driving controller configured to control operations of the scan driver and the data driver, and to provide a clock signal to the scan driver;
• and
• a buffer circuit configured to compensate for distortion of the clock signal, and
• wherein the buffer circuit comprises:
• a pull-up transistor connected between a first voltage source and an output node;
• a pull-down transistor connected between the output node and a second voltage source;
• and
• at least one voltage boosting circuit configured to receive the clock signal, to generate a boosting signal by amplifying an amplitude of the clock signal, and to transmit the boosting signal to a gate electrode of the pull-down transistor.