Shift register, driving method, gate driving circuit and display device
AssigneesChengdu Boe Optoelectronics Technology Co., Ltd., Boe Technology Group Co., Ltd.
InventorsYipeng Chen, Ling Shi
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Abstract
A shift register, a driving method, a gate driving circuit and a display device are provided. In the shift register, a first maintenance sub-circuit is coupled to a control signal input end and a first node, and configured to substantially maintain a voltage at the first node in a first operating mode. A second maintenance sub-circuit is coupled to the control signal input end and a second node, and configured to substantially maintain a voltage at the second node in the first operating mode.
Claims20
A shift register, comprising a first node, a second node, a first output sub-circuit, and a second output sub-circuit, wherein the shift register further comprises a first maintenance sub-circuit and/or a second maintenance sub-circuit;
- the first output sub-circuit is coupled to a first level signal input end, a gate driving signal output end and the first node, and configured to control the first level signal input end to be electrically coupled to or electrically decoupled from the gate driving signal output end under the control of the first node;
- the second output sub-circuit is coupled to a first clock signal input end, the gate driving signal output end and the second node, and configured to control the first clock signal input end to be electrically coupled to or electrically decoupled from the gate driving signal output end under the control of the second node;
- the first maintenance sub-circuit is coupled to a control signal input end and the first node, and configured to substantially maintain a voltage at the first node in a first operating mode;
- and
- the second maintenance sub-circuit is coupled to the control signal input end and the second node, and configured to substantially maintain a voltage at the second node in the first operating mode.
A gate driving circuit, comprising a plurality of cascaded shift registers, wherein the shift register comprises a first node, a second node, a first output sub-circuit, and a second output sub-circuit, wherein the shift register further comprises a first maintenance sub-circuit and/or a second maintenance sub-circuit;
- the first output sub-circuit is coupled to a first level signal input end, a gate driving signal output end and the first node, and configured to control the first level signal input end to be electrically coupled to or electrically decoupled from the gate driving signal output end under the control of the first node;
- the second output sub-circuit is coupled to a first clock signal input end the gate driving signal output end and the second node. and configured to control the first clock signal input end to be electrically coupled to or electrically decoupled from the gate driving signal output end under the control of the second node;
- the first maintenance sub-circuit is coupled to a control signal input end and the first node. and configured to substantially maintain a voltage at the first node in a first operating mode;
- and
- the second maintenance sub-circuit is coupled to the control signal input end and the second node, and configured to substantially maintain a voltage at the second node in the first operating mode.
Dependencies are inferred from the claim text.