Neural processing device

A neural processing device, comprising:

• at least one first CGRA engine, each of which comprises a PE array comprising a plurality of processing elements, an L0 memory configured to store data for the PE array, an instruction memory configured to provide an instruction for an operation of the plurality of processing elements, and an LSU (load store unit) configured to perform load and store operations for the data;
• a first L1 memory shared by the at least one first CGRA engine;
• and
• a first L1 interconnection configured to transmit data between the first L1 memory and the at least one first CGRA engine, wherein
• the at least one first CGRA engine is managed by a sequencer,
• the sequencer is configured to individually provide hardware resource to the at least one first CGRA engine according to importance, and
• the hardware resource comprises at least one of voltage, power, temperature, or frequency.

A processing element included in at least one CGRA engine, wherein the at least one CGRA engine is included in a CGRA engine group, and the CGRA engine group is individually provided with hardware resource by a sequencer, the processing element comprising:

• an instruction queue configured to receive an instruction set architecture, the instruction set architecture comprising a precision including a first precision for input data, a second precision required for an operation, and a third precision required for output, a source comprising an operand, an opcode comprising an operator, and a destination comprising location information to which output data is transmitted;
• a first register configured to receive the source, the first precision, and the second precision from the instruction queue;
• an input formatter configured to determine the operand through the first register and to perform precision conversion based on the first precision and the second precision;
• a second register configured to receive the opcode from the instruction queue and to determine the operator;
• and a third register configured to receive the destination, the second precision, and the third precision from the instruction queue,
• wherein the hardware resource comprise at least one of voltage, power, temperature, or frequency.