Neural processing circuit with concurrent image processing and non-maximum suppression
AssigneeDeepx Co., Ltd.
InventorHo Chul LEE
Life of this patent
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Abstract
According to one example of the present disclosure, the neural processing unit may comprise a processing element array configured to perform operations of a neural network model and a post-processing unit configured to process data output from the processing element array. The post-processing unit includes a first computation circuit that extracts a subset of classes for each bounding box by comparing class scores of classes and a second computation circuit configured to extract one or more bounding boxes by comparing a class confidence score of each bounding box with a threshold confidence score.
Claims20
A neural processing circuit comprising:
- a processing element array circuit configured to generate data output by performing operations of a neural network model;
- and
- a post-processing circuit coupled to the processing element array circuit, the post-processing circuit comprising an internal memory and an internal processing circuit,
- wherein in a first period, the processing element array circuit generates a first data output from a first image, the post-processing circuit extracts a first subset of the first data output, and the internal memory stores the first subset of the first data output, and
- wherein in a second period subsequent to the first period, the processing element array circuit generates a second data output from a second image subsequent to the first image, and the internal processing circuit performs a non-maximum suppression (NMS) operation on the first subset of the first data output stored in the internal memory.
A method for processing a neural network model in a neural processing circuit, the method comprising:
- generating, by a processing element array circuit, a first data output by performing operations of the neural network model on a first image during a first period;
- extracting, by a post-processing circuit coupled to the processing element array circuit, a first subset of the first data output;
- storing the first subset in an internal memory of the post-processing circuit during the first period;
- generating, by the processing element array circuit, a second data output by performing operations of the neural network model on a second image during a second period subsequent to the first period;
- and
- performing, by an internal processing circuit of the post-processing circuit, a non-maximum suppression (NMS) operation on the first subset of the first data output stored in the internal memory during the second period.
A neural processing circuit comprising:
- a processing element array circuit configured to sequentially process a plurality of images using a neural network model to generate bounding box data for each of the plurality of images;
- and
- a post-processing circuit comprising an internal memory and an internal processing circuit, the post-processing circuit configured to extract a subset of the bounding box data for a respective image and store the subset in the internal memory,
- wherein the neural processing circuit is configured to operate in a pipelined manner such that the internal processing circuit performs a non-maximum suppression (NMS) operation on the subset of the bounding box data corresponding to a first image of the plurality of images concurrently with the processing element array circuit processing a second image of the plurality of images, the second image being subsequent to the first image.
Dependencies are inferred from the claim text.