Integrated circuit device

A method of manufacturing an integrated circuit device, the method comprising:

• forming a superlattice barrier on a substrate, the superlattice barrier having a multilayered structure in which different kinds of material layers are alternately stacked one by one,
• forming a channel layer on the superlattice barrier;
• defining a fin-type active region in the substrate by etching portions of each of the channel layer, the superlattice barrier, and the substrate;
• forming a plurality of dummy gate structures on the channel layer;
• forming a plurality of channel regions from the channel layer by removing portions of the channel layer using the plurality of dummy gate structures as etch masks;
• forming a recess by etching a portion of the superlattice barrier between a pair of dummy gate structures selected from the plurality of dummy gate structures;
• and
• forming a source/drain region in the recess, the source/drain region being in contact with the superlattice barrier.

A method of manufacturing an integrated circuit device, the method comprising:

• forming a superlattice barrier by alternately stacking a plurality of first sub-layers and a plurality of second sub-layers one by one on a substrate, each of the plurality of first sub-layers including a semiconductor layer doped with oxygen atoms, and each of the plurality of second sub-layers including an undoped semiconductor layer;
• forming a structure on the superlattice barrier, the structure comprising a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers alternately stacked one by one on the superlattice barrier;
• defining a fin-type active region in the substrate by etching portions of each of the structure, the superlattice barrier, and the substrate;
• forming a plurality of dummy gate structures on the channel layer;
• forming a plurality of outer insulating spacers covering both sidewalls of each of the plurality of dummy gate structures;
• forming a plurality of nanosheet stacks from the plurality of nanosheet semiconductor layers by removing portions of the structure using the plurality of dummy gate structures and the plurality of outer insulating spacers as etch masks;
• forming a recess by etching a portion of the superlattice barrier between a pair of dummy gate structures selected from the plurality of dummy gate structures;
• and
• forming a source/drain region in the recess, the source/drain region being in contact with the superlattice barrier.

A method of manufacturing an integrated circuit device, the method comprising:

• forming a superlattice barrier on a substrate, wherein the superlattice barrier comprises a plurality of first sub-layers and a plurality of second sub-layers alternately stacked one by one, each of the plurality of first sub-layers comprises a semiconductor layer doped with oxygen atoms, each of the plurality of second sub-layers comprising an undoped semiconductor layer, and the semiconductor layer and the undoped semiconductor layer comprise germanium;
• forming a structure on the superlattice barrier, the structure comprising a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers alternately stacked one by one on the superlattice barrier;
• defining a fin-type active region in the substrate by etching portions of each of the structure, the superlattice barrier, and the substrate;
• forming a plurality of dummy gate structures on the channel layer;
• forming a plurality of nanosheet stacks from the plurality of nanosheet semiconductor layers by removing portions of the structure using the plurality of dummy gate structures as etch masks;
• forming a recess by etching a portion of the superlattice barrier between a pair of dummy gate structures selected from the plurality of dummy gate structures;
• and
• forming a source/drain region in the recess, the source/drain region being in contact with the superlattice barrier.