Palettization of kernel vector with look-up tables in neural network processor
AssigneeApple Inc.
InventorSung Hee Park
Life of this patent
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Abstract
Embodiments of the present disclosure relate to a neural processor circuit including a kernel access circuit and at least a neural engine circuit including output channels. The kernel access circuit can access kernel data including a first look-up table (LUT) and a second LUT. The neural engine circuit can further include a kernel extract circuit configured to extract the first LUT from the kernel data and assign the first LUT for computing outputs of output channels of a first output channel group (OCG) of the output channels, and extract the second LUT from the kernel data and assign the second LUT for computing outputs of output channels of a second OCG of the output channels.
Claims20
A neural processor circuit, comprising:
- a kernel access circuit configured to access kernel data comprising:
- a first look-up table (LUT) having a first plurality of entries;
- a second LUT having a second plurality of entries;
- and
- index data comprising a plurality of indices;
- and
- a neural engine circuit comprising a plurality of output channels and configured to receive the kernel data from the kernel access circuit, wherein the neural engine circuit comprises a kernel extract circuit configured to:
- extract the first LUT and the index data from the kernel data and assign the first LUT and the index data for computing outputs of output channels of a first output channel group (OCG) of the plurality of output channels;
- and
- extract the second LUT from the kernel data and assign the second LUT and the index data for computing outputs of output channels of a second OCG of the plurality of output channels.
A method of operating a neural processor circuit, comprising:
- accessing, by a kernel access circuit, kernel data comprising:
- a first look-up table (LUT) having a first plurality of entries;
- a second LUT having a second plurality of entries;
- and
- index data comprising a plurality of indices;
- extracting, by a kernel extract circuit of a neural engine circuit, the first LUT, the second LUT, and the index data from the kernel data;
- assigning the first LUT and the index data for computing outputs of output channels of a first output channel group (OCG) of a plurality of output channels of the neural engine circuit;
- assigning the second LUT and the index data for computing outputs of output channels of a second OCG of the plurality of output channels;
- and
- performing, by a multiply-add (MAD) circuit coupled to the kernel extract circuit, neural network operations on input data based on the first LUT for computing the outputs for output channels of the first OCG at a first time instance and for computing the outputs for output channels of the second OCG at a second time instance.
An electronic device, comprising:
- a system memory storing input data;
- and
- a kernel access circuit configured to access kernel data comprising:
- a first look-up table (LUT) having a first plurality of entries;
- a second LUT having a second plurality of entries;
- and
- index data comprising a plurality of indices;
- and
- a neural engine circuit comprising a plurality of output channels and configured to receive the kernel data from the kernel access circuit, wherein the neural engine circuit comprises:
- a kernel extract circuit configured to:
- extract the first LUT and the index data from the kernel data and assign the first LUT and the index data for computing outputs of output channels of a first output channel group (OCG) of the plurality of output channels;
- and
- extract the second LUT from the kernel data and assign the second LUT and the index data for computing outputs of output channels of a second OCG of the plurality of output channels;
- and
- a multiply-add (MAD) circuit coupled to the kernel extract circuit and configured to perform neural network operations on the input data stored in the system memory based on the first LUT for computing the outputs for output channels of the first OCG at a first time instance and for computing the outputs for output channels of the second OCG at a second time instance.
Dependencies are inferred from the claim text.