CXL Scale-Up Memory Tier for GPUs and Heterogeneous PCIe Fabrics Comprising Hosts, Devices, and Switches, Enabling Shared Memory via Protocol Translations

An apparatus for translating between Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs) and Compute Express Link (CXL) messages, comprising:

• a first interface configured to communicate with a first entity based on PCIe;
• a second interface configured to communicate with a second entity based on CXL.mem;
• and
• a computer coupled to the first interface and the second interface, wherein the computer is configured to:
• receive a PCIe memory request from the first entity via the first interface;
• translate the PCIe memory request to a CXL.mem Master-to-Subordinate (M2S) request;
• send, to the second entity via the second interface, the CXL.mem M2S request;
• receive, from the second entity via the second interface, a CXL.mem Subordinate-to-Master Data Response (S2M DRS) corresponding to the CXL.mem M2S request;
• translate the CXL.mem S2M DRS to a PCIe Completion;
• and
• send the PCIe Completion to the first entity via the first interface.

A system comprising:

• Graphics Processing Units (GPUs), wherein at least one GPU of the GPUs does not support Compute Express Link (CXL) communications;
• a CXL device coupled to memory having a capacity greater than a capacity of high-bandwidth memory (HBM) of any one of the GPUs;
• and
• a computer coupled between the GPUs and the CXL device, the computer comprising:
• a first interface configured to communicate with the GPUs based on PCIe;
• and
• a second interface configured to communicate with the CXL device based on CXL.mem;
• wherein the computer is configured to:
• receive, from a GPU of the GPUs via the first interface, a PCIe memory request;
• translate the PCIe memory request to a CXL.mem Master-to-Subordinate (M2S) request;
• send, to the CXL device via the second interface, the CXL.mem M2S request;
• receive, from the CXL device via the second interface, a CXL.mem Subordinate-to-Master Data Response (S2M DRS);
• translate the CXL.mem S2M DRS to a PCIe Completion;
• and
• send the PCIe Completion to the GPU via the first interface.