Processor with CXL Scale-Up Networking over IEEE 802.3 PMA for Memory Pooling and KV Caching in AI Infrastructures

Abstract

Implementations disclose a processor architecture with an integrated resource provisioning unit (RPU) for CXL protocol translation over a physical layer based on IEEE 802.3 PMA. An apparatus comprises an IC package with processing cores coupled to a memory controller, memory channels coupled to memory, a physical layer based on IEEE 802.3 PMA to communicate with an external entity, and an RPU comprising a CXL device. The RPU translates between CXL-based protocol data units communicated via the CXL device and carrier protocol PDUs encapsulating data indicative of CXL opcodes and physical addresses transmitted and received via the IEEE 802.3 PMA. The RPU may enable external entities to access the processor's memory, or enable the processing cores to access resources coupled to external entities. The carrier protocol PDUs may include encapsulating headers with routing, sequencing, and multi-tenancy fields.

Dependencies are inferred from the claim text.