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US 2026/0228141 A1Published application
Multi-chip package and computing system using the same
AssigneeSK hynix Inc.
InventorsSeong Ju LEE, Yangsoo PARK, Sunjoo KIM
Life of this patent
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Abstract
A computing system includes a host, a main memory, and a storage apparatus. During a first operation mode, the host accesses the main memory and the storage apparatus, respectively. During a second operation mode, the host directly moves data between the main memory and the storage apparatus.
Claims21
A computing system comprising:
- a host;
- a main memory;
- a storage memory;
- and
- a storage controller coupled to the host, the main memory, and the storage memory,
- wherein the storage controller is configured to read first data from the main memory based on a computation command address signal received from the host and is configured to perform a computation on the first data.
3 more elements
A computing system comprising:
- a host coupled to a first memory bus;
- a first memory chip comprising a first pseudo channel coupled to the first memory bus and a second pseudo channel coupled to a second memory bus;
- a second memory chip comprising a first pseudo channel coupled to the second memory bus and a second pseudo channel coupled to the first memory bus;
- and
- a storage controller coupled to the host, the second memory bus, and a storage bus and coupled to a storage memory through the storage bus,
- wherein the storage controller is configured to read first data from the first and second memory chips through the second memory bus based on a computation command address signal provided from the host and configured to perform a first computation on the first data, and
- wherein the host is configured to provide a first memory command address signal to the first and second memory chips to read second data from the first and second memory chips through the first memory bus and configured to perform a second computation on the second data.
4 more elements
A computing system comprising:
- a host coupled to a first memory bus;
- a first memory chip comprising a first pseudo channel coupled to the first memory bus and a second pseudo channel coupled to a second memory bus;
- a second memory chip comprising a first pseudo channel coupled to the second memory bus and a second pseudo channel coupled to the first memory bus;
- and
- a storage controller coupled to the host, the second memory bus, and a storage bus and coupled to a storage memory through the storage bus,
- wherein the storage controller is configured to read first data from the first and second memory chips through the second memory bus based on a computation command address signal provided from the host and configured to perform a first computation on the first data, and
- wherein the host is configured to provide a first memory command address signal through the first memory bus to perform a data input/output operation with the first and second memory chips.
4 more elements
Dependencies are inferred from the claim text.