Enhanced system detection design of solid-state drives (ssd) for hot-plug capability
AssigneeMicron Technology, Inc.
InventorHuayu Chen
Life of this patent
Estimating the term…
Abstract
A processing device in a memory system receives, from a host system, a reference clock signal and a reset signal. The processing device determines whether the reference clock signal satisfies a first initialization criterion and the reset signal satisfies a second initialization criterion. Responsive to determining that the reference clock signal and reset bit satisfy the respective initialization criteria, the processing device initializes a data transfer interface with the host system.
Claims20
A system comprising:
- a memory device;
- and
- a processing device, operatively coupled to the memory device, to perform operations comprising:
- receiving, from a host system, a reference clock signal and a reset signal;
- determining whether the reference clock signal satisfies a first initialization criterion and the reset signal satisfies a second initialization criterion;
- and
- responsive to determining that the reference clock signal satisfies the first initialization criterion and the reset signal satisfies the second initialization criterion, initializing a data transfer interface with the host system.
A method comprising:
- receiving, from a host system, a reference clock signal and a reset signal;
- determining whether the reference clock signal satisfies a first initialization criterion and the reset signal satisfies a second initialization criterion;
- and
- responsive to determining that the reference clock signal satisfies the first initialization criterion and the reset signal satisfies the second initialization criterion, initializing a data transfer interface with the host system.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- receiving, from a host system, a reference clock signal and a reset signal;
- determining whether the reference clock signal satisfies a first initialization criterion and the reset signal satisfies a second initialization criterion;
- and
- responsive to determining that the reference clock signal satisfies the first initialization criterion and the reset signal satisfies the second initialization criterion, initializing a data transfer interface with the host system.
Dependencies are inferred from the claim text.