Device and method for protecting information leakage from the bus

A processing unit housed on a chip, comprising:

• a microprocessor for reading and/or writing in an external memory via a bus, the external memory being arranged outside the chip,
• an address protection unit that comprises
• a swap unit implementing an address permutation scheme to protect information leakage from the bus,
• a permutation table maintaining a mapping between real address called by the microprocessor and masked address used by the swap unit to address the external memory,
• a shuffle buffer containing M slots among N slots of a memory address space of the external memory, wherein M<N,
• a counter table containing one counter per slot of said N slots, wherein a counter of a slot is incremented only when an element of said slot is written in the shuffle buffer,
• wherein, in response to a call, from the microprocessor, of a first element contained in the external memory, the swap unit is configured to
• emit a read call at masked address A to the external memory and get a ciphertext of the first element and a tag of the first element;
• verify, decrypt and write the first element in the shuffle buffer at a randomly picked address A′ where a second element was stored;
• encrypt said second element using the counter of said second element so as to generate a ciphertext and a tag for said second element, and write the ciphertext and a tag for said second element in the external memory at address A;
• note down in the permutation table;
• increment only the counter of the first element once the tag of said first element has been verified.