Fast modulo processing for interleaved memory having non-power-of-two channels

A network-on-chip (NoC) comprising:

• a transport interconnect;
• a target network interface unit (NIU) configured for interleaved N-channels system memory, where N is not a power of two;
• and
• a plurality of initiator NIUs for communicating with the target NIU via the transport interconnect;
• wherein at least one of the NIUs is configured to process an address to calculate a modulo N of an M-bit address without performing division-by-N, wherein the modulo N of the address is calculated as [Σi ai mod N*2bi mod N]mod N, where Σiai*2bi represents the M-bit address, ai is an ith word in the address, 2bi is a power of two associated with the ith word, and mod N of 2bi=1 for all i;
• wherein in a first level of the processing, ai(mod N) for each i is calculated to produce a number P of remainders;
• wherein at least one intermediate level of the processing is performed to reduce the P remainders to a single intermediate word, where each intermediate level of the processing includes forming word groups from the remainders of a previous level and performing modulo N operations on the word groups;
• and
• wherein in a last level of the processing, a modulo N of the single intermediate word is calculated.

A system on chip (SoC) comprising:

• system memory having N interleaved channels, where N is not a power of two;
• and
• a network-on-chip having a plurality of network interface units;
• wherein at least one of the network interface units is configured to:
• receive a request to access the system memory, the request including an M-bit address;
• and
• process the address to calculate a modulo N of the address without performing division-by-N, wherein the modulo N of the address is calculated as [Σi ai mod N*2bi mod N]mod N, where Σi ai*2bi represents the M-bit address, ai is an ith word in the address, 2bi is a power of two associated with the ith word, and mod N of 2bi=1 for all i;
• wherein:
• in a first level of processing, ai(mod N) for each i is calculated;
• in at least one intermediate level of processing, remainders from a previous level are formed into intermediate word groups, and modulo N operations are performed on the intermediate word groups until a single intermediate word is formed;
• and
• in a last level of processing, a modulo N of the single intermediate word is performed.