Back to results
US 2026/0228129 A1Published application
Bank mapping for memory
AssigneeMicron Technology, Inc.
InventorRobert M. Walker
Life of this patent
Estimating the term…
Abstract
Mapping addresses to banks can include receiving a plurality of row bits, a plurality of column bits, and a plurality of bank bits and generating a rank bit from a bank bit from the plurality of bank bits. Updated bank bits can be generated by removing the bank bit from the plurality of bank bits. The plurality of row bits, the plurality of column bits, the rank bit, and the updated bank bits can be provided to the controller to access a plurality of banks of the memory device.
Claims20
An apparatus, comprising:
- memory device;
- a controller coupled to the memory device, wherein the controller is configured to support up to a particular quantity of banks, and wherein the memory device comprises a quantity of banks that is greater than the particular quantity of banks;
- mapping logic coupled to the controller and configured to generate a second memory address based on a first memory address comprising a plurality of row bits, a plurality of column bits, and a plurality of bank bits, wherein the second memory address is generated by:
- multiplexing a bank bit of the plurality of bank bits of the first memory address to a rank bit in the second memory address, and
- using remaining bank bits of the plurality of bank bits as updated bank bits such that the second memory address comprises the plurality of row bits, the plurality of column bits, the rank bit, and the updated bank bits.
2 more elements
A method, comprising:
- receiving, at mapping logic of a memory sub-system, a rank bit, a plurality of row bits, a plurality of column bits, and a plurality of bank bits;
- generating, at the mapping logic, a row bit from a bank bit of the plurality of bank bits and updated bank bits;
- generating, at the mapping logic, updated row bits by adding the row bit to the plurality of row bits wherein the row bit is as a least significant bit of the updated row bits;
- and
- accessing, utilizing a controller of the memory sub-system, a first memory device and a second memory device of the memory sub-system utilizing the rank bit, the updated row bits, the plurality of column bits, and the updated bank bits,
- wherein the first memory device and the second memory device comprises a quantity of banks that is greater than a particular quantity of banks supported by the controller.
3 more elements
An apparatus, comprising:
- a memory device comprising a plurality of banks;
- and
- a controller configured to support up to a particular quantity of banks that is less than the plurality of banks, wherein the controller is configured to:
- access a first bank of the plurality of banks responsive to receipt of a first address without a rank bit;
- access a second bank of the plurality of banks responsive to receipt of a second address having the rank bit;
- access the first bank utilizing a first updated address that maps a bank bit of the first address to the rank bit, wherein updated bank bits of the first updated address are generated by removing the bank bit from a plurality of bank bits of the first address and wherein the bank bit is a most significant bit from the plurality of bank bits;
- and
- access the second bank utilizing a second updated address that maps a bank bit of the second address to a row bit.
5 more elements
Dependencies are inferred from the claim text.