Fault recovery of peripheral input/output lines

A system-on-chip (SoC), comprising:

• one or more processing cores;
• and
• a peripheral interconnect subsystem coupled between the one or more processing cores and one or more slave devices, wherein the peripheral interconnect subsystem comprises:
• at least one input/output controller coupled to the one or more slave devices via a set of input/output lines, wherein the at least one input/output controller is configured to control data transfer between at least one processing core of the one or more processing cores and the one or more slave devices via the set of input/output lines;
• and
• at least one monitoring circuit coupled to the set of input/output lines, wherein the at least one monitoring circuit is configured to:
• generate a control signal having a first state based on a deviation of at least one input/output line of the set of input/output lines from a default state;
• and
• generate an interrupt based on the control signal having the first state upon a lapse of a time-period.