Memory Fault Prediction Method and Apparatus, Chip, Device, and Storage Medium

A chip, comprising:

• a logic circuit configured to:
• obtain a first error location distribution of an error correction unit associated with a memory, wherein the memory comprises at least one memory device, herein the at least one memory device comprises a plurality of memory cells arranged in a first array, wherein the error correction unit comprises a plurality of data bits obtained from the memory cells through a plurality of consecutive times of burst read, wherein each of the data bits corresponds to one memory cell in the memory cells, wherein the first error location distribution indicates a location of an error data bit in the data bits, and wherein the first error location distribution causes correctable error (CE) occurrence in the memory;
• obtain a memory fault model comprising at least one reference location distribution, wherein the at least one reference location distribution is associated with an uncorrectable error (UCE) of the memory;
• and
• output a prediction result based on a first similarity between the first error location distribution and the at least one reference location distribution, wherein the prediction result indicates a probability of UCE occurrence in the memory;
• and
• a power supply circuit configured to supply power to the logic circuit.

An electronic device, comprising:

• one or more memory storages configured to store instructions;
• and
• one or more processors coupled to the one or more memory storages, wherein when executed by the one or more processors, the instructions cause the electronic device to:
• obtain a first error location distribution of an error correction unit associated with a memory, wherein the memory comprises at least one memory device, wherein the at least one memory device comprises a plurality of memory cells arranged in a first array, wherein the error correction unit comprises a plurality of data bits obtained from the memory cells through a plurality of consecutive times of burst read, wherein each of the data bits corresponds to one memory cell in the plurality of memory cells, wherein the first error location distribution indicates a location of an error data bit in the data bits, and wherein the first error location distribution causes correctable error (CE) occurrence in the memory;
• obtain a memory fault model comprising at least one reference location distribution, wherein the at least one reference location distribution is associated with an uncorrectable error (UCE) of the memory;
• and
• output a prediction result based on a first similarity between the first error location distribution and the at least one reference location distribution,
• wherein the prediction result indicates a probability of UCE occurrence in the memory.