Apparatus for implementing data-driven synchronization in task-parallel and barrier synchronization in data-parallel programs

An apparatus (100) for implementing data-driven synchronization in task-parallel and barrier synchronization in data-parallel programs for execution by a processing system with software-managed coherence, comprising:

• a plurality of compute elements (CEs) (102-1 to 102-N) configured for cooperative execution of a program composed of tasks, wherein a task is one of a compute-task and service-task, wherein compute tasks are exclusively executed on the plurality of CEs (102-1 to 102-N), and service tasks are employed for implementing barrier synchronization in data-parallel programs, wherein tasks dependency is specified through synchronization instructions;
• On-chip memory subsystem with private caches of each CE at level-1 (Private L1 Cache) (104-1 to 104-N) and a shared cache at level-2 (L2 Shared Cache) (108) with software-managed coherence, where coherence between Private L1 Cache (104-1 to 104-N) and L2 Shared cache (108) is ensured through explicit flush and invalidation of L1 cache blocks;
• a synchronization unit (110) configured to maintain a list of records implemented in hardware, wherein each record is associated with a task comprising a state information of the task, wherein a state information includes one of a ready state, a waiting state and a running state, wherein a task is configured to create or update records in the list of records using the synchronization instructions;
• and
• a task dispatcher (112) configured to dispatch one or more compute tasks for execution on one more CEs of the plurality of CEs (102-1 to 102-N) based on the record list, wherein the task dispatcher 112 is configured to implement barrier synchronization using service tasks, wherein the task dispatcher 112 is configured to signal one or more CEs to resume execution of stalled compute tasks based on the status of a corresponding service tasks, wherein the plurality of CEs (102-1 to 102-N), the on-chip memory subsystem, the synchronization unit 108, and the task dispatcher 112 are communicatively coupled to each other.