Control processor based central processing unit (cpu) core enablement for faster cold/quick boot
AssigneeQUALCOMM Incorporated
InventorsDinesh Kumar CHOUDHARY, Maulik SHAH
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Abstract
A processor-implemented method of control processor based central processing unit (CPU) cores for faster cold/quick boot includes executing a cold boot process for a primary processor of multiple processors. The primary processor and cluster components firmware for supporting the multiple processors are enabled. A set of secondary processors of the multiple processors is enabled for software instruction fetching. The set of secondary processors of the multiple processors is configured to start execution of software instructions from a temporary wrapper.
Claims20
An apparatus, comprising:
- at least one memory;
- and
- multiple processors coupled to the at least one memory, at least one processor of the multiple processors being configured to:
- execute a cold boot process for a primary processor of the multiple processors;
- enable the primary processor and cluster components firmware for supporting the multiple processors;
- enable a set of secondary processors of the multiple processors for software instruction fetching;
- and
- configure the set of secondary processors of the multiple processors to start execution of software instructions from a temporary wrapper.
A processor-implemented method performed by one or more processors, the processor-implemented method comprising:
- executing a cold boot process for a primary processor of multiple processors;
- enabling the primary processor and cluster components firmware for supporting the multiple processors;
- enabling a set of secondary processors of the multiple processors for software instruction fetching;
- and
- configuring the set of secondary processors of the multiple processors to start execution of software instructions from a temporary wrapper.
An apparatus, comprising:
- means for executing a cold boot process for a primary processor of multiple processors;
- means for enabling the primary processor and cluster components firmware for supporting the multiple processors;
- means for enabling a set of secondary processors of the multiple processors for software instruction fetching;
- and
- means for configuring the set of secondary processors of the multiple processors to start execution of software instructions from a temporary wrapper.
Dependencies are inferred from the claim text.