Multi-vector renaming to avoid bank write conflicts
AssigneeQUALCOMM Incorporated
InventorsVinay PATEL, Luca MARONCELLI, Yiran HUANG
Life of this patent
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Abstract
Techniques proposed herein may dynamically map architectural registers that instructions use to a set of physical registers from different rename banks, rather than using the same architectural registers as specified in an instruction set architecture (ISA). For example, each architectural register that the instructions use may be renamed to a physical register from a different rename bank. A rename bank refers to a set of physical registers that are used to store values for the instructions. A processor keeps track of the renaming of the architectural registers in a table.
Claims20
A method, comprising:
- obtaining a sequence of instructions that includes at least one instruction that has at least one operand that references multiple architectural register tags;
- renaming the multiple architectural register tags to physical register tags organized in multiple rename banks;
- and
- dispatching the instruction for execution after the renaming.
An apparatus, comprising:
- a memory comprising instructions;
- and
- one or more processors, individually or collectively, configured to execute the instructions and cause the apparatus to:
- obtain a sequence of instructions that includes at least one instruction that has at least one operand that references multiple architectural register tags;
- rename the multiple architectural register tags to physical register tags organized in multiple rename banks;
- and
- dispatch the instruction for execution after the renaming.
A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to perform a method, comprising:
- obtaining a sequence of instructions that includes at least one instruction that has at least one operand that references multiple architectural register tags;
- renaming the multiple architectural register tags to physical register tags organized in multiple rename banks;
- and
- dispatching the instruction for execution after the renaming.
Dependencies are inferred from the claim text.