Processor core, operation method thereof, and processing system

An operation method of a processor core, the operation method comprising:

• detecting a first read modify write (RMW) instruction among a plurality of instructions stored in a program memory;
• computing a memory address of the first RMW instruction;
• queuing the first RMW instruction in an RMW queue;
• based on the first RMW instruction having no dependency on a preceding instruction, processing a load operation associated with the first RMW instruction;
• processing a compute operation for modifying the data loaded into a register based on a load operation;
• processing a store operation for storing the modified data into a memory;
• dequeuing the first RMW instruction from the RMW queue;
• and
• parallelly processing a second independent RMW instruction subsequent to the first RMW instruction while data stored in the memory is being loaded into the register based on the load operation.

A processing system, comprising:

• a processor core comprising a register, a general-purpose load store unit (LSU) circuit and a read modify write (RMW) circuit;
• a system bus;
• and
• a memory,
• wherein, subsequent to the RMW circuit processing a load operation in response to a first RMW instruction and while data is loaded from the memory to the register based on a load operation associated with the first RMW instruction, the processor core is configured to control the RMW circuit or the general-purpose LSU circuit to process a subsequent independent instruction having no dependency on the first RMW instruction.