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US 2026/0227958 A1Published application
Adaptive fault injection facilitation systems, methods, and computer program products
AssigneeIOActive Inc.
InventorsGabriel GONZALEZ, Ramiro PAREJA-VEREDAS
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Abstract
Systems, methods, and computer program products are disclosed in regard to selectively adapting a subset of parametric test sequences respectively applied to multiple units-in-test (UITs). After an anomaly is exhibited by a first UIT undergoing a first parametric sequence but not by a second UIT undergoing a second parametric sequence. Adaptive coordination across UITs is thereby enabled, allowing streamlined sequence selection and expanded detection coverage. Related systems and computer program products configured to facilitate this coordinated validation process are also described.
Claims19
An adaptively parallelized coordinated validation method comprising:
- invoking first transistor-based circuitry configured to establish numerous special-purpose controllers operably coupled to a single local host that include a first special-purpose controller operably coupled with and configured to implement a first parametric sequence upon a first unit in test (UIT) at least by virtue of said first special-purpose controller deterministically generating numerous respective sets of glitch attempt parameters based on first device-executable code provided by a remote entity and configured locally and that include a second special-purpose controller operably coupled with and configured to implement a second parametric sequence upon a second UIT by virtue of said second special-purpose controller deterministically generating its glitch attempt parameters likewise based on said first device-executable code;
- automatically invoking second transistor-based circuitry configured to obtain a first test result indicating one or more flaw-indicative anomalies of said first parametric sequence upon said first UIT;
- and
- automatically invoking third transistor-based circuitry configured to cause said second special-purpose controller to implement said first parametric sequence upon said second UIT partly based on said one or more flaw-indicative anomalies of said first parametric sequence upon said first UIT and partly based on an indication that no flaw-indicative anomalies have yet been detected by said second special-purpose controller.
1 more element
A coordinated validation method comprising:
- invoking first transistor-based circuitry configured to establish numerous special-purpose controllers operably coupled to a single local host that include a first special-purpose controller operably coupled with and configured to implement a first parametric sequence upon a first unit in test (UIT) and that include a second special-purpose controller operably coupled with and configured to implement a second parametric sequence upon a second UIT by virtue of said second special-purpose controller deterministically generating its glitch attempt parameters based on said first device-executable code;
- invoking second transistor-based circuitry configured to obtain a first test result indicating one or more flaw-indicative anomalies of said first parametric sequence upon said first UIT;
- and
- invoking third transistor-based circuitry configured to cause said second special-purpose controller to implement said first parametric sequence upon said second UIT partly based on said one or more flaw-indicative anomalies of said first parametric sequence upon said first UIT and partly based on an indication that no flaw-indicative anomalies have yet been detected by said second special-purpose controller.
1 more element
A coordinated validation system comprising:
- first transistor-based circuitry configured to establish numerous special-purpose controllers operably coupled to a single local host that include a first special-purpose controller operably coupled with and configured to implement a first parametric sequence upon a first unit in test (UIT) and that include a second special-purpose controller operably coupled with and configured to implement a second parametric sequence upon a second UIT by virtue of said second special-purpose controller deterministically generating its glitch attempt parameters based on said first device-executable code;
- second transistor-based circuitry configured to obtain a first test result indicating one or more flaw-indicative anomalies of said first parametric sequence upon said first UIT;
- and
- third transistor-based circuitry configured to cause said second special-purpose controller to implement said first parametric sequence upon said second UIT partly based on said one or more flaw-indicative anomalies of said first parametric sequence upon said first UIT and partly based on an indication that no flaw-indicative anomalies have yet been detected by said second special-purpose controller.
1 more element
Dependencies are inferred from the claim text.