Efficient high-precision matrix multiply operations

A hardware circuit for performing floating-point matrix multiplication operations, the hardware circuit comprising:

• an exponent extraction circuit configured to extract exponent components from floating-point values in a first vector from a first input matrix and a second vector from a second input matrix;
• an Exponent Cancellation Degree (ECD) calculator circuit configured to calculate an ECD value representing a difference between a sum of a first maximum exponent value from the first vector and a second maximum exponent value from the second vector, and a third maximum exponent value obtained from summing corresponding element exponents across the first vector and the second vector;
• a guard bit determination circuit configured to determine a required number of guard bits based on the ECD value;
• an Extended Bit Count (EBC) calculator circuit configured to calculate an EBC requirement by adding a mantissa bit width defined by a specified floating-point format to the required number of guard bits;
• a selector circuit configured to select a dot product operation between an integer-based dot product operation and a floating-point dot product operation based on whether the integer-based dot product operation with the required number of guard bits provides faster execution than the floating-point dot product operation while maintaining required precision;
• an integer matrix multiplication accelerator (IMMA) circuit having a configurable bit width allocation for processing integer-based dot product operations, wherein a bit width allocation is dynamically configured according to the EBC;
• and
• a result processing circuit configured to generate and store a floating-point scalar value in an output matrix, using the dot product operation.

A processor implementing instruction set architecture (ISA) support for dynamic guard bit calculation in floating-point matrix multiplication, the processor comprising:

• an instruction decoder configured to decode an Exponent Cancellation Degree (ECD) calculation instruction specifying at least a first source register containing exponent values from a first vector, a second source register containing exponent values from a second vector, and a destination register;
• execution circuit coupled to the instruction decoder, the execution circuit configured to:
• calculate sums of corresponding exponent values from the first source register and the second source register;
• determine a maximum or minimum of the sums based on instruction-specified operation type;
• and
• store a result in the destination register for use in determining required guard bits for integer-based matrix multiplication operations;
• and
• register file circuit coupled to the execution circuit, the register file circuit configured to provide source operands to the execution circuit and receive computation results from the execution circuit.