US 2026/0227918 A1Published application

Per-rank power management operations for a multi-rank memory system

AssigneeMicron Technology, Inc.

InventorAntonino CAPRI'

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Abstract

In some implementations, a memory controller may determine that an idle timer for a rank of a memory channel satisfies a first threshold. The memory controller may transition, based on determining that the idle timer for the rank satisfies the first threshold, the rank from a first power state to a second, lower power state, wherein at least one other rank of the memory channel is maintained in the first power state. The memory controller may determine that an activation trigger has occurred, wherein the activation trigger includes at least one of: determining, by the memory controller, that a reduced-power timer satisfies a second threshold, or receiving, by the memory controller, a command associated with the rank. The memory controller may transition the rank from the second power state to the first power state in response to determining that the activation trigger has occurred.

Claims24

Dependent claims

A method, comprising:

determining, by a memory controller of a memory system, that an idle timer for a rank of a memory channel, of multiple ranks of the memory channel, satisfies a first threshold;
transitioning, by the memory controller and based on determining that the idle timer for the rank satisfies the first threshold, the rank from a first power state to a second power state,
wherein the second power state is lower than the first power state, and
wherein at least one other rank of the memory channel is maintained in the first power state while the rank is transitioned from the first power state to the second power state;
determining, by the memory controller, that an activation trigger has occurred,
wherein the activation trigger includes at least one of:
determining, by the memory controller, that a reduced-power timer satisfies a second threshold, or
receiving, by the memory controller, a command associated with the rank;
and
transitioning, by the memory controller, the rank from the second power state to the first power state in response to determining that the activation trigger has occurred.

7 more elements

A multi-rank memory system, comprising:

multiple memory components organized into multiple memory channels, each memory channel associated with multiple ranks;
and
a memory controller operatively connected to the multiple memory components, wherein the memory controller is configured to:
determine that an idle timer for a rank of a memory channel, of the multiple ranks of the memory channel, satisfies a first threshold;
transition, based on determining that the idle timer for the rank satisfies the first threshold, the rank from a first power state to a second power state,
wherein the second power state is lower than the first power state, and
wherein at least one other rank of the memory channel is maintained in the first power state while the rank is transitioned from the first power state to the second power state;
determine that an activation trigger has occurred,
wherein the activation trigger includes at least one of:
a determination that a reduced-power timer satisfies a second threshold, or
reception of a command associated with the rank;
and
transition the rank from the second power state to the first power state in response to determining that the activation trigger has occurred.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/437,140Filed 30 Dec 2025
Priority: 31 Jan 2025
Published: 6 Aug 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 3/0625
Specifically adapted to achieve a particular effect: power saving in storage systems
G06F 3/0655
Making use of a particular technique: vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more…
Y02D 10/00
Energy efficient computing
G06F
Computing and data processing