Memories having segmented data lines
AssigneeMicron Technology, Inc.
InventorsVikas Rana, Kalyan Chakravarthy Kavalipurapu
Life of this patent
Estimating the term…
Abstract
Memories might include an array of memory cells, a data line having a first data line segment selectively connected to a second data line segment and selectively connected to a plurality of memory cells of the array of memory cells, and a controller for access of the array of memory cells. The controller might be configured to cause the memory to selectively enable programming of a data state of a memory cell of the array of memory cells through a first connection to the first data line segment, and to read the data state of the memory cell through a second connection, different than the first connection, to the second data line segment.
Claims20
A memory, comprising:
- an array of memory cells;
- a data line selectively connected to a plurality of memory cells of the array of memory cells, wherein the data line comprises a first data line segment and a second data line segment, and wherein the second data line segment is selectively connected to the first data line segment;
- and
- a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
- selectively enable programming of a data state of a memory cell of the plurality of memory cells through a first connection to the first data line segment;
- and
- read the data state of the memory cell through a second connection, different than the first connection, to the second data line segment.
A memory, comprising:
- an array of memory cells;
- and
- a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
- enable a memory cell of the array of memory cells for programming using a first page buffer;
- program a data state of the memory cell;
- and
- read the data state of the memory cell using a second page buffer.
A memory, comprising:
- an array of memory cells;
- a data line comprising a plurality of data line segments, wherein each data line segment of the plurality of data line segments is selectively connected to each immediately adjacent data line segment of the plurality of data line segments through a respective switch of one or more switches;
- and
- a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
- connect a memory cell of the array of memory cells to a first data line segment of the plurality of data line segments through a second data line segment of the plurality of data line segments, wherein the memory cell is selectively connected to the second data line segment without passing through any switch of the one or more switches, and wherein the memory cell is selectively connected to the first data line segment through at least one switch of the one or more switches;
- enable the memory cell for programming using a first page buffer of a first type of page buffer selectively connected to the first data line segment without passing through any switch of the one or more switches;
- program a data state of the memory cell;
- after programming the data state of the memory cell, connect the memory cell to the second data line segment, and isolate the memory cell from the first data line segment;
- and
- read the data state of the memory cell using a second page buffer of a second type of page buffer, different than the first type of page buffer, selectively connected to the second data line segment without passing through any switch of the one or more switches.
Dependencies are inferred from the claim text.