Stack memory devices communicating via packets
AssigneeSK hynix Inc.
InventorChoung Ki SONG
Life of this patent
Estimating the term…
Abstract
A stack memory device includes a physical layer configured to receive write data, a write valid signal, and a transmission write clock signal from an external device and transmit read data, a read valid signal, and a transmission read clock signal to the external device, a selector configured to output a signal output from the physical layer through a first channel or a second channel, based on a channel selection signal, and a control layer configured to receive an output signal of the selector through the first channel or the second channel to generate a control command and an address for controlling a write operation or a read operation within a core chip.
Claims20
A semiconductor system comprising:
- a processor configured to transmit external packet data;
- and
- a semiconductor device electrically connected to the processor and configured to receive the external packet data,
- wherein the semiconductor device
- receives the external packet data to generate internal packet data,
- decodes the internal packet data to extract internal data, and
- writes the internal data to a core chip when a write operation is performed on the core chip.
A semiconductor system comprising:
- a processor configured to transmit external packet data;
- and
- a semiconductor device electrically connected to the processor and configured to receive the external packet data,
- wherein the semiconductor device
- receives the external packet data to generate internal packet data,
- decodes the internal packet data to generate read data based on internal data output from the core chip when a read operation is performed on the core chip, and
- transmits the read data to the processor.
A semiconductor system comprising:
- a processor;
- and
- a semiconductor device electrically connected to the processor,
- wherein the semiconductor device
- receives external packet data from the processor through a first interface,
- generates internal packet data from the external packet data,
- decodes the internal packet data to extract first internal data through a second interface, and
- writes the first internal data when a write operation is performed on a core chip.
A semiconductor system comprising:
- a processor configured to transmit a command and first data;
- and
- a semiconductor device electrically connected to the processor,
- wherein the semiconductor device comprises:
- a base chip;
- and
- a core chip stacked with the base chip and electrically connected to the base chip through through-vias,
- wherein the base chip decodes the command to write the first data to the core chip when a write operation is performed on the core chip.
Dependencies are inferred from the claim text.