# US 2026/0227663 A1 · Liquid crystal display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0227663 A1 - Document ID: US20260227663A1 - Status: Published application - Kind: A1 - Application number: 18/695,837 - Filed: 2024-02-18 - Published: 2026-08-06 - Earliest claimed: 2024-02-04 - Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd. - Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd. - Inventors: Xiaochen LI; Xiaoxu LIAN - Web page: https://patentgrep.com/patent/US20260227663A1 ## CPC - G02F 1/136209: {Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element} - G02F 1/133512: {Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence)} - G02F 1/13394: {spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence)} - G02F 1/1362: Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} - G02F 1/13624: {having more than one switching element per pixel} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract Embodiments of the present disclosure disclose a liquid crystal display panel. In the liquid crystal display panel of the embodiments of the present disclosure, in an orthographic projection pattern of the liquid crystal display panel, first shielding portions of a black matrix layer completely cover adjacent two scanning lines, thin film transistor connected to the adjacent two scanning lines, and paddings. ## Claims ### Claim 1 A liquid crystal display panel comprising: a black matrix layer provided with a plurality of pixel openings, wherein the black matrix layer comprises a plurality of first shielding portions disposed along a first direction, and the first shielding portions are disposed between adjacent two rows of pixel openings; an array substrate comprising a plurality of pixel electrodes, a plurality of scanning lines disposed along the first direction, and a plurality of thin film transistors; wherein the pixel electrodes are disposed corresponding to the pixel openings; in an orthographic projection pattern of the liquid crystal display panel, adjacent two scanning lines are disposed between adjacent two rows of pixel openings, and the first shielding portions cover the scanning lines and the thin film transistors; and the scanning lines are connected to gates of the thin film transistors; and a plurality of paddings disposed on the array substrate, wherein in the orthographic projection pattern of the liquid crystal display panel, the first shielding portions cover the paddings. ### Claim 2 (depends on 1) The liquid crystal display panel of claim 1, wherein the black matrix layer further comprises a plurality of third shielding portions, the array substrate further comprises a plurality of common electrode lines extending along the first direction, and the third shielding portions cover the common electrode lines; wherein two rows of pixel openings are disposed between adjacent two first shielding portions, and one of the common electrode lines is disposed between two rows of pixel openings and between two first shielding portions. ### Claim 3 (depends on 2) The liquid crystal display panel of claim 2, wherein a width of the third shielding portions is less than a width of the first shielding portions m1. ### Claim 4 (depends on 2) The liquid crystal display panel of claim 2, wherein the array substrate further comprises a plurality of data lines disposed along a second direction intersecting with the first direction; in the orthographic projection pattern of the liquid crystal display panel, the data lines intersect with the scanning lines and the common electrode lines respectively; one of the pixel electrodes comprises a first pixel electrode and a second pixel electrode; the first pixel electrode corresponds to one of the pixel openings, the second pixel electrode corresponds to one of the pixel openings; one of the scanning lines comprises a first scanning line and a second scanning line; one of the thin film transistors comprises a first thin film transistor and a second thin film transistor; a gate of the first thin film transistor is connected to the first scanning line, a gate of the second thin film transistor is connected to the second scanning line, an output pole of the first thin-film transistor is connected to the first pixel electrode, and an output pole of the second thin-film transistor is connected to the second pixel electrode; one of the common electrode lines is spaced between a side of the first pixel electrode away from the first thin-film transistor and a side of the second pixel electrode away from the second thin-film transistor, and the first scanning line and the second scanning line are spaced between a side of the first pixel electrode close to the first thin film transistor and a side of the second pixel electrode close to the second thin film transistor; and the black matrix layer comprises a plurality of second shielding portions, and the first shielding portions intersect with and are connected to the second shielding portions; wherein in the orthographic projection pattern of the liquid crystal display panel, one of the first shielding portions, one of the pixel openings, one of the third shielding portions, and another one of the pixel openings are alternately arranged in a direction perpendicular to the first direction, and the second shielding portions cover the data lines. ### Claim 5 (depends on 4) The liquid crystal display panel of claim 4, wherein in the orthographic projection pattern of the liquid crystal display panel, the plurality of paddings are arranged in rows along the first direction, and a row of first pixel electrodes and a row of second pixel electrodes are disposed between adjacent two rows of the paddings in the direction perpendicular to the first direction. ### Claim 6 (depends on 4) The liquid crystal display panel of claim 4, wherein in the orthographic projection pattern of the liquid crystal display panel, one of the paddings is disposed at an intersection of one of the first shielding portions and one of the second shielding portions; and the paddings partially overlap with the first scanning line, the second scanning line, and one of the data lines. ### Claim 7 (depends on 6) The liquid crystal display panel of claim 6, wherein in the orthographic projection pattern of the liquid crystal display panel, in the direction perpendicular to the first direction, a region where the paddings are located has a first width, a region where the first scanning line and the first thin film transistor connected thereto are located has a second width, a region where the second scanning line and the second thin film transistor connected thereto are located has a third width, and the first width is greater than the second width and the third width and less than or equal to a sum of the second width and the third width. ### Claim 8 (depends on 7) The liquid crystal display panel of claim 7, wherein in the orthographic projection pattern of the liquid crystal display panel, the first thin-film transistor is disposed at a side of the first scanning line away from the second scanning line, and the second thin-film transistor is disposed at a side of the second scanning line away from the first scanning line and aligned with the first thin-film transistor. ### Claim 9 (depends on 8) The liquid crystal display panel of claim 8, wherein the first scanning line comprises a first main line and at least one first extension portion, wherein the first extension portion is connected to a side of the first main line away from the second scanning line and the gate of the first thin film transistor; and the first thin film transistor comprises a first active layer, and in the orthographic projection pattern of the liquid crystal display panel, the first active layer overlaps with the gate of the first thin film transistor. ### Claim 10 (depends on 9) The liquid crystal display panel of claim 9, wherein the first active layer extends along an extension direction of the first main line, an extension direction of the first extension portion intersects with the extension direction of the first main line, and the first active layer overlaps with two first extension portions. ### Claim 11 (depends on 6) The liquid crystal display panel of claim 6, wherein in the orthographic projection pattern of the liquid crystal display panel, the first thin film transistor partially overlaps with the second thin film transistor along the first direction; one of the first shielding portions comprises a base and a row shielding portion connected to the base; wherein in the orthographic projection pattern of the liquid crystal display panel, the base completely covers one of the paddings, the base covers a part of one of the scanning lines and one of the thin film transistors, and the row shielding portion covers another part of the one of the scanning lines and the one of the thin film transistors; wherein a width of the base is greater than a width of the row shielding portion in the direction perpendicular to the first direction. ### Claim 12 (depends on 11) The liquid crystal display panel of claim 11, wherein the first thin film transistor comprises a first active layer, wherein the first active layer comprises a first portion and a second portion connected to the first portion, and an extension direction of the first portion intersects with an extension direction of the second portion; and the first scanning line overlaps with the first portion and the second portion, and a part of the first scanning line overlapping with the first portion and the second portion is multiplexed as the gate of the first thin film transistor. ### Claim 13 (depends on 12) The liquid crystal display panel of claim 12, wherein the first scanning line comprises a plurality of first turning portions and a first connecting portion connected between adjacent two first turning portions, and each of the first turning portions comprises a first segment, a second segment, and a third segment sequentially connected to each other; wherein an extension direction of the first segment intersects with an extension direction of the second segment, the extension direction of the second segment intersects with an extension direction of the third segment; and both of the first segment and the third segment are connected to a side of the second segment close to the second scanning line, an end of the first connecting portion is connected to the first segment of one of the first turning portions, and another end of the first connecting portion is connected to the third segment of another one of the first turning portions; and the first connecting portion overlaps with the first portion, and the first segment overlaps with the second portion. ### Claim 14 (depends on 13) The liquid crystal display panel of claim 13, wherein the second thin film transistor comprises a second active layer, wherein the second active layer comprises a third portion and a fourth portion connected to the third portion, and an extension direction of the third portion intersects with an extension direction of the fourth portion; and the second scanning line overlaps with the third portion and the fourth portion, and a part of the second scanning line overlapping with the third portion and the fourth portion is multiplexed as the gate of the second thin film transistor. ### Claim 15 (depends on 14) The liquid crystal display panel of claim 14, wherein the second scanning line comprises a plurality of second turning portions and a second connecting portion connected between adjacent two second turning portions, and each of the second turning portions comprises a fourth segment, a fifth segment, and a sixth segment sequentially connected to each other; wherein an extension direction of the fourth segment intersects with an extension direction of the fifth segment, the extension direction of the fifth segment intersects with an extension direction of the sixth segment; and both of the fourth segment and the sixth segment are connected to a side of the fifth segment away from the first scanning line, an end of the second connecting portion is connected to the fourth segment of one of the second turning portions, and another end of the second connecting portion is connected to the sixth segment of another one of the second turning portions; and the fourth segment overlaps with the third portion, and the fifth segment overlaps with the fourth portion. ### Claim 16 (depends on 15) The liquid crystal display panel of claim 15, wherein the first turning portions are aligned with the second turning portions in the direction perpendicular to the first direction, and the first connecting portion is aligned with the second connecting portion; and along the first direction, the extension direction of the fifth segment and an extension direction of the first connecting portion are the same, the fifth segment and the first connecting portion are alternately arranged, and the fifth segment is aligned with the first connecting portion. ### Claim 17 (depends on 16) The liquid crystal display panel of claim 16, wherein the first portion intersects with and is connected to the third portion, the first thin film transistor and the second thin film transistor share a common input pole, and the common input pole is connected to one of the data lines and connected to an intersection of the first portion and the third portion. ### Claim 18 (depends on 17) The liquid crystal display panel of claim 17, wherein one of the data lines is connected to the common input pole through a first via, and in the orthographic projection pattern of the liquid crystal display panel, one of the data lines, the first via, and the common input pole are disposed overlapping with each other. ### Claim 19 (depends on 17) The liquid crystal display panel of claim 17, wherein the output pole of the first thin-film transistor and the output pole of the second thin-film transistor are adjacent in a region defined by one of the first turning portions and the fifth segment, and the common input pole is disposed between the first connecting portion and the second connecting portion. ### Claim 20 (depends on 6) The liquid crystal display panel of claim 6, further comprising an opposing substrate disposed opposite to the array substrate, wherein the black matrix layer is integrated into the opposing substrate or the array substrate, and the paddings are integrated into the opposing substrate or the array substrate.