Controlling testability of a true complement dynamic circuit

A method comprising:

• configuring a first circuit to perform a Boolean logic, the first circuit configured to receive via bit lines, a first input signal and a second input signal, wherein the first input signal and the second input signal are dynamic signals that are complementary signals during an evaluation phase, the first circuit further configured to receive a third input signal and a fourth input signal via data lines;
• receiving, by a second circuit, an enable test signal as an input to the second circuit;
• and
• using the enable test signal, controlling, by the second circuit, a logical behavior of the first circuit by controlling the third input signal received at the first circuit.

A method comprising:

• configuring a first circuit to perform a Boolean logic, the first circuit configured to receive via bit lines, a first input signal and a second input signal, wherein the first input signal and the second input signal are dynamic signals that are complementary signals during an evaluation phase, the first circuit further configured to receive a third input signal and a fourth input signal via data lines;
• receiving, by a second circuit, an enable test signal;
• and
• using the enable test signal, controlling, by the second circuit, a logical behavior of the first circuit by controlling the fourth input signal received at the first circuit.