Reduction of gate-drain capacitance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJung-Hung Chang, Lo-Heng Chang, Zhi-Chang Lin, Shih-Cheng Chen, Kuo-Cheng Chiang, Chih-Hao Wang
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Abstract
A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
Claims20
A semiconductor device, comprising:
- a bottom dielectric feature disposed on a substrate;
- nanostructures disposed over the bottom dielectric feature;
- a gate structure wrapping around each of the nanostructures and interfacing a top surface of the bottom dielectric feature;
- a first epitaxial feature disposed over the substrate;
- and
- a second epitaxial feature disposed over the first epitaxial feature and interfacing end sidewalls of the nanostructures,
- wherein a sidewall of the bottom dielectric feature is spaced apart from the first epitaxial feature by a liner.
A semiconductor device, comprising:
- a bottom dielectric feature disposed on a substrate;
- channel members disposed over the bottom dielectric feature;
- inner spacer features interleaving the channel members;
- a gate structure wrapping around each of the channel members;
- a first epitaxial feature disposed over and interfacing the substrate;
- a second epitaxial feature disposed over the first epitaxial feature and interfacing end sidewalls of the channel members;
- and
- a liner extending between a sidewall of the bottom dielectric feature and the first epitaxial feature,
- wherein a bottommost one of the inner spacer features is spaced apart from the sidewall of the bottom dielectric feature by the liner.
A semiconductor device, comprising:
- a bottom dielectric feature disposed on a substrate;
- nanostructures disposed over the bottom dielectric feature;
- a gate structure wrapping around each of the nanostructures and interfacing a top surface of the bottom dielectric feature;
- a first epitaxial feature disposed over the substrate;
- a second epitaxial feature disposed over the first epitaxial feature and interfacing end sidewalls of the nanostructures;
- and
- a liner extending between a sidewall of the bottom dielectric feature and the first epitaxial feature,
- wherein the nanostructures extend lengthwise along a first direction,
- wherein the gate structure extends lengthwise along a second direction different from the first direction,
- wherein the bottom dielectric feature comprises a sheet-like gap,
- wherein the sheet-like gap extends along a plane defined by the first direction and the second direction.
Dependencies are inferred from the claim text.