Semiconductor device gate structure

A method, comprising:

• forming a first plurality of nanostructured channel layers on a substrate;
• forming a second plurality of nanostructured channel layers on the substrate;
• etching gate openings surrounding the first and second pluralities of nanostructured channel layers;
• depositing a dielectric layer within the gate openings;
• forming a dummy layer between nanostructured channel layers of the first plurality of nanostructured channel layers;
• depositing work function metal layer in the gate openings surrounding the first and second pluralities of nanostructured channel layers;
• removing the work function layer from the gate openings surrounding the first plurality of nanostructured channel layers;
• and
• removing the dummy layer formed between the nanostructured channel layers of the first plurality of nanostructured channel layers.

A device, comprising:

• a first transistor comprising:
• a first set of nanostructured channel layers disposed on a substrate;
• and
• a first gate structure surrounding the first set of nanostructured channel layers and comprising:
• a first oxide layer formed on exposed surfaces of the first set of nanostructured channel layers;
• a first dielectric layer in contact with the first oxide layer;
• a work function layer in contact with the first dielectric layer;
• and
• a gate contact layer in contact with the work function layer;
• and
• a second transistor comprising:
• a second set of nanostructured channel layers disposed on the substrate;
• and
• a second gate structure surrounding the second set of nanostructured channel layers comprising:
• a second oxide layer formed on exposed surfaces of the second set of nanostructured channel layers;
• and
• a second dielectric layer in contact with the second oxide layer and the gate contact layer, wherein
• the second dielectric layer is on a top surface of an uppermost nanostructured channel layer of the second set of nanostructured channel layers and has a first thickness,
• the second dielectric layer is disposed on a bottom surface of the uppermost nanostructured channel layer of the second set of nanostructured channel layers and has a second thickness, and
• the second thickness is greater than the first thickness.