Semiconductor device structure and methods of forming the same

A semiconductor device structure, comprising:

• a first source/drain region, wherein the first source/drain region comprises a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with a dopant, a concentration of the dopant in the first epitaxial layer is different from a concentration of the dopant in the second epitaxial layer, and a thickness of the first source/drain region is different from a width of the first source/drain region in a cross-sectional view;
• a first semiconductor layer disposed adjacent the first source/drain region;
• a second semiconductor layer disposed over the first semiconductor layer;
• a gate structure disposed over the second semiconductor layer, wherein the gate structure comprises a gate dielectric layer;
• a first spacer having a first sidewall interfacing the gate dielectric layer and a second sidewall facing away from the gate structure;
• a contact etch stop layer (CESL) disposed facing the second sidewall of the first spacer;
• and
• a second source/drain region disposed over the first source/drain region, wherein an air gap is formed between the first and second source/drain regions.

A method, comprising:

• forming a fin structure over a substrate;
• forming a sacrificial gate structure on a portion of the fin structure;
• and
• recessing an exposed portion of the fin structure to form a source/drain recess, wherein the exposed portion of the fin structure is recessed by a cyclic etching process, the cyclic etching process comprises performing a plurality of cycles, and each cycle comprises:
• a plasma formation stage;
• an etch stage;
• and
• a purge stage, wherein a shape of the source/drain recess is controlled by adjusting a ratio of a time duration of the purge stage to a time duration of the plasma formation and etch stages.