Interfacial layer between channels and inner spacers for performance boost of nanostructure transistors
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Yu LIN, Chang-Yun CHANG, Yen-Ting CHEN
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Abstract
A method for forming an integrated circuit includes forming a plurality of stacked channels of a transistor and forming a plurality of interfacial dielectric structures each in contact with one of the channels. The method includes forming a plurality of inner spacers interleaved with the channels. The method includes forming a gate metal wrapped around the channels. After forming the gate metal, each inner spacer is in contact with a respective interfacial dielectric structure positioned between the inner spacer and an adjacent channel of the plurality of channels.
Claims20
A method, comprising:
- forming a plurality of stacked channels of a transistor;
- forming a plurality of interfacial dielectric structures each in contact with one of the channels;
- forming, after forming the interfacial dielectric structures, a plurality of inner spacers interleaved with the channels;
- and
- forming a gate metal wrapped around the channels, wherein after forming the gate metal each inner spacer is connected with a respective interfacial dielectric structure positioned between the inner spacer and an adjacent channel of the plurality of channels.
A device, comprising:
- a transistor including:
- a plurality of stacked channels;
- a gate dielectric layer wrapped around and in contact with central portions of the channels;
- a gate metal wrapped around the channels and separated from the channels by the gate dielectric layer;
- a plurality of inner spacers interleaved with end portions of the channels;
- a source/drain region connected with each of the channels;
- and
- a plurality of interfacial dielectric structures each positioned in contact with one of the inner spacers and an adjacent channel, the interfacial dielectric structures are laterally between the gate metal and the source/drain region.
A method, comprising:
- forming first and second stacked channels of a transistor;
- forming an inner spacer between the first and second stacked channels;
- forming a first interfacial dielectric structure between a top surface of the inner spacer and a bottom surface of the first channel;
- forming a second interfacial dielectric structure between a bottom surface of the inner spacer and a top surface of the second channel;
- forming a gate dielectric wrapped around the first and second stacked channels;
- and
- forming a gate metal wrapped around the first and second stacked channels.
Dependencies are inferred from the claim text.