Charge trapping not or (nor) flash memory architectures

A method for operating a memory device, comprising:

• programming a memory cell of a memory array, wherein programming the memory cell comprises:
• biasing a first word line of a plurality of word lines with a first voltage, wherein the first word line is coupled with the memory cell;
• biasing one or more second word lines of the plurality of word lines with a second voltage that is less than the first voltage;
• and
• biasing a first pillar of a plurality of pillars of the memory array with a third voltage that is less than the second voltage, the first pillar being coupled with the memory cell, wherein a charge is stored in the memory cell in accordance with biasing the first word line with the first voltage, biasing the one or more second word lines with the second voltage, and biasing the first pillar with the third voltage.

A memory device, comprising:

• one or more memory arrays;
• and
• processing circuitry coupled with the one or more memory arrays and configured to cause the memory device to:
• program a memory cell of the one or more memory arrays, wherein, to program the memory cell, the processing circuitry is configured to cause the memory device to:
• bias a first word line of a plurality of word lines with a first voltage, wherein the first word line is coupled with the memory cell;
• bias one or more second word lines of the plurality of word lines with a second voltage that is less than the first voltage;
• and
• bias a first pillar of a plurality of pillars of the one or more memory arrays with a third voltage that is less than the second voltage, the first pillar being coupled with the memory cell, wherein a charge is stored in the memory cell in accordance with biasing the first word line with the first voltage, biasing the one or more second word lines with the second voltage, and biasing the first pillar with the third voltage.