Resource reservation in latency constrained packet transmission networks

A method for determining total aggregation delay of aggregated bursts of packets along a candidate path for a prospective virtual circuit in a latency constrained packet transmission network having one or more existing virtual circuits, the latency constrained packet transmission network governed by a network management system and having a plurality of interconnected switches each having one or more ingress ports and one or more egress ports, the method comprising:

• a) identifying for each egress port along the candidate path of the prospective virtual circuit a largest packet size of each existing virtual circuit along the candidate path having an egress queue priority higher than or equal to an egress queue priority of the prospective virtual circuit;
• b) identifying a largest packet size of the prospective virtual circuit;
• c) determining a maximum arrival time as a sum of the largest packet size of each existing virtual circuit and the largest packet size of the prospective virtual circuit, divided by an ingress port speed of the ingress port paired with the egress port;
• d) identifying a set of existing virtual circuits utilizing the same egress port as the prospective virtual circuit and a different ingress port from the prospective virtual circuit, the set of existing virtual circuits further having an egress queue priority higher than or equal to the egress queue priority of the prospective virtual circuit;
• e) determining for each ingress port a receipt time of a largest packet size of each existing virtual circuit in the set of existing virtual circuits by dividing the largest packet size of each existing virtual circuit in the set of existing virtual circuits by an ingress port speed of the associated ingress port;
• f) defining an ordered descending set of the receipt times of each existing virtual circuit in the set of existing virtual circuits;
• g) summing sequentially from highest to lowest each receipt time of the ordered descending set of the receipt times until summing a sequential receipt time would exceed the maximum arrival time;
• h) selecting a set of packet sizes corresponding to each receipt time in the sum of the ordered descending set of the receipt times of each existing virtual circuit in the set of existing virtual circuits;
• i) determining an initial egress delay as a sum of the largest packet sizes of each existing virtual circuit along the candidate path having an egress queue priority higher than or equal to the prospective virtual circuit and the set of packet sizes, divided by the egress port speed of the associated egress port, and then further reduced by the maximum arrival time;
• j) identifying a subset of existing virtual circuits of the set of existing virtual circuits, wherein the subset of existing virtual circuits is limited to the existing virtual circuits having an egress queue priority higher than the egress queue priority of the prospective virtual circuit;
• k) determining for each ingress port a receipt time of a largest packet size of each existing virtual circuit in the subset of existing virtual circuits by dividing the largest packet size of each existing virtual circuit in the subset of existing virtual circuits by an ingress port speed of the associated ingress port;
• l) defining an ordered descending subset of the receipt times of each existing virtual circuit in the subset of existing virtual circuits excluding the receipt times summed in step (g);
• m) summing sequentially from highest to lowest each receipt time of the ordered descending subset of receipt times until summing a subsequent receipt time would exceed the initial egress delay;
• n) selecting a subset of packet sizes corresponding to each receipt time in the sum of the ordered descending subset of the receipt times of each existing virtual circuit in the subset of existing virtual circuits;
• o) determining a subsequent egress delay as a sum of the subset of packet sizes divided by the egress port speed of the associated egress port;
• p) repeating steps (l) through (o) in an iterative process, substituting the subsequent egress delay determined in step (o) of each prior iteration for the initial egress delay in step (m) until the subsequent egress delay determined in step (o) is equal to zero;
• q) retaining a total subsequent egress delay comprising a sum of each subsequent egress delay determined in step (p);
• r) determining the total aggregation delay as a sum of the initial egress delay and the total subsequent egress delay.