Correction of phase interpolator and delay-locked loop errors in clock and data recovery loop

A device for compensating phase interpolation errors in a clock and data recovery (CDR) loop, the device comprising:

• means for generating a correction table based on a distribution of phase interpolator (PI)-codes generated by the CDR loop, wherein the correction table corrects a non-linearity in the distribution;
• means for receiving a PI-code for a PI;
• and
• means for selecting a corrected PI-code for the PI, the corrected PI-code associated with the received PI-code in the correction table.

A receiver configured to correct non-linearity in a clock and data recovery (CDR) loop, the receiver comprising:

• an analog subsystem comprising:
• an analog-to-digital converter (ADC);
• and
• a phase interpolator (PI) coupled to the ADC, the PI to generate a phase-adjusted clock signal for the ADC based on a PI-code;
• a PI-code accumulator in the CDR loop, the PI-code accumulator to generate a PI-code for the PI to select a phase offset for the phase-adjusted clock signal;
• and
• a PI-code corrector coupled between the PI-code accumulator and the PI, the PI-code corrector to generate a corrected PI-code based on the PI-code from the PI-code accumulator, wherein the corrected PI-code corrects for a non-linearity in the PI.