Encoder
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWin-San Khwa, Hiroki Noguchi, Ku-Feng Lin
Life of this patent
Estimating the term…
Abstract
An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.
Claims20
A method comprising:
- receiving, by a first stage, a first input;
- decoding, by the first stage, the first input;
- producing, by the first stage, a first output comprising the decoded first input;
- receiving, by a second stage, a second input;
- receiving, by the second stage, the first output from the first stage;
- converting, by the second stage, the first output and the second input from a first code to a second code based on the second input and the first output;
- and
- producing, by the second stage, a second output comprising the converted first output and the converted second input.
A method comprising:
- receiving a first input comprising a 0th bit, a 1st bit, a 2nd bit, and a 3rd bit of an input code;
- decoding the 0th bit, the 1st bit, and the 2nd bit of the input code;
- producing a first output comprising the decoded first input on seven output nodes on the 7:1 decoder;
- and
- converting, by a plurality of two input port AND gates, the first output from the input code to a second code, wherein each one of the plurality of two input port AND gates comprises a first input port respectively connected to one of seven output nodes of the 7:1 decoder and a second input port connected to an inverse of trd 3rd bit of the input code.
An apparatus comprising:
- a first stage configured to;
- receiving a 0th bit, a 1st bit, and a 2nd bit of an input code, and
- decoding the 0th bit, the 1st bit, and the 2nd bit of the input code to create a first output;
- and
- a second stage configured to:
- receive the first output from the first stage,
- received a 3rd bit of the input code,
- convert the first output to a second code based on 3rd bit, and
- generate a second output comprising from the converted first output and the 3rd bit of the input code.
Dependencies are inferred from the claim text.