Fractional feedback divider for fractional-n phase locked loop
AssigneeMarvell Asia Pte Ltd
InventorsJingjing Deng, Wenjie Zheng, Xin Zhang
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Abstract
A fractional-N phase locked loop (PLL) is described and includes a voltage-controlled oscillator (VCO) configured to output a VCO clock signal and a fractional feedback divider (FFD) connected to an output of the VCO, the FFD receiving the VCO clock signal and a feedback divider ratio, the feedback divider ratio comprising an integer portion and a fractional portion. The FFD further includes a multi-modulus divider (MMD) configured to divide the VCO clock signal by N or N+1; and a phase interpolator (PI) connected to an output of the MMD, the PI configured to interpolate between a first phase signal and a second phase signal to adjust an output phase of a feedback clock signal.
Claims20
A fractional-N phase locked loop (PLL), comprising:
- a voltage-controlled oscillator (VCO) configured to output a VCO clock signal;
- a fractional feedback divider (FFD) connected to an output of the VCO, the FFD receiving the VCO clock signal and a feedback divider ratio, the feedback divider ratio comprising an integer portion and a fractional portion, the FFD further comprising:
- a multi-modulus divider (MMD) configured to divide the VCO clock signal by N or N+1;
- and
- a phase interpolator (PI) connected to an output of the MMD, the PI configured to interpolate between a first phase signal and a second phase signal to adjust an output phase of a feedback clock signal.
A fractional feedback divider (FFD) connected to receive a voltage-controlled oscillator (VCO) clock signal and a feedback divider ratio comprising an integer portion and a fractional portion, the FFD comprising:
- a multi-modulus divider (MMD) configured to divide the VCO clock signal by N or N+1, where N is equal to the integer portion of the feedback divider ratio;
- a modulator configured to control operation of the MMD, wherein when an output of the modulator is equal to zero, the MMD divides the VCO clock signal by N and when the output of the modulator is equal to one, the MMD divides the VCO clock signal by N+1;
- and
- a phase interpolator (PI) connected to receive an output of the MMD, the PI configured to interpolate between a first phase signal and a second phase signal to adjust an output phase of a feedback clock signal.
An apparatus for generating a feedback clock signal based on a voltage-controlled oscillator (VCO) clock signal and a feedback divider ratio comprising an integer portion and a fractional portion, the circuit comprising:
- first circuitry for dividing the VCO clock signal by N or N+1 to create a divided VCO clock signal, where N is equal to the integer portion of the feedback divider ratio;
- second circuitry configured accumulate the fractional portion of the feedback divider ratio and to output a control signal to the first circuitry, wherein when the control signal is equal to zero, the first circuitry divides the VCO clock signal by N and when the control signal is equal to one, the first circuitry divides the VCO clock signal by N+1;
- and
- third circuitry for interpolating between a first phase signal and a second phase signal to adjust an output phase of a feedback clock signal, wherein the first and second phase signals are based on the divided VCO clock signal.
Dependencies are inferred from the claim text.