US 2026/0221977 A1 · FREQUENCY-STABLE, LOW-NOISE TIMING SIGNAL GENERATOR HAVING MULTIPLE MEMS RESONATORS AND NESTED-PLL STRUCTURE

Abstract

A frequency synthesizer uses an oven-controlled oscillator (“OCXO”) to generate a reference signal. A nested-PLL structure features an outer PLL loop with a divider that implements temperature correction of the output of the OCXO, to thereby form a temperature-compensated OCXO (“TCOCXO”); this divider also is dependent on information that selects a frequency for synthesis. An oscillation source of the outer PLL loop is implemented as an inner PLL loop of the nested-PLL structure; this inner PLL loop use an output of a second oscillator (“SXO”) as its reference frequency and an electronic VCO. The nested-PLL structure is designed such that phase noise from the TCOCXO dominates a synthesized frequency output for low frequencies, phase noise from the SXO dominates at mid-range frequencies, and phase noise from the electronic VCO dominates at high frequencies.

Claims26

Dependent claims

A timing signal generator, comprising:

a first oscillator (FXO);
a second oscillator (SXO);
a first phase-locked loop (PLL) to receive an output of the FXO and to generate a first signal therefrom;
and
a second PLL to receive an output of the SXO and to generate a second signal therefrom, wherein the second PLL comprises an oscillation source that is at least partially dependent on an electronic voltage controlled oscillator (VCO), and wherein the second PLL comprises a divider that is controlled in dependence upon the first signal;
wherein the timing signal generator is to output a timing signal dependent on the second signal.

3 more elements

A timing signal generator, comprising:

a first oscillator, wherein the first oscillator is an oven-controlled oscillator (OCXO), and wherein the first oscillator comprises at least one microelectromechanical systems (MEMS) resonator and at least one structure to serve as a temperature sensor;
a second oscillator (SXO);
a first phase-locked loop (PLL) to receive an output of the OCXO and to generate a first signal therefrom, wherein the first PLL has a divider;
and
a second PLL to receive an output of the SXO and to generate a second signal therefrom, wherein the second PLL comprises an oscillation source that is at least partially dependent on an electronic voltage controlled oscillator (VCO), and wherein the second PLL comprises a divider that is controlled in dependence on the first signal;
wherein the timing signal generator is to output a timing signal dependent on the second signal.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/145,991Filed 25 Jan 2024

Priority

30 Jan 2023

Published

30 Jul 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H03L 7/0991
Concerning mainly the controlled oscillator of the loop: the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed…
H03L 7/1976
For fractional frequency division: using a phase accumulator for controlling the counter or frequency divider
G01K 7/32
Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using…: using…
H03L 1/022
Against variations of temperature only: by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the…

Frequency-stable, low-noise timing signal generator having multiple mems resonators and nested-pll structure

Life of this patent

Frequency-stable, low-noise timing signal generator having multiple mems resonators and nested-pll structure

Life of this patent

Abstract

Claims26