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AssigneeMurata Manufacturing Co., Ltd.
InventorsRobert Mark ENGLEKIRK, Keith RAMPMEIER, Arpita Moghe CHADHA
Estimating the term…
Circuits and methods for determining the characteristics of swappable pins in a peripheral in a 1-Wire or similar single-conductor system, thereby allowing each one of two pins to be either an I/O pin (connected to an I/O line) or a CAP pin (connected to a storage capacitor). Embodiments may utilize a hybrid buffer circuit that utilizes an effectively bi-directional PFET pull-up device coupled between the swappable pins A and B. Two open-drain NFETs pull-down devices are used, one on either side of the PFET and coupled to a respective pin (A or B), but with only one NFET being selected to be operable based on pin-determination flag signals from the pin detection circuitry. Such a hybrid buffer circuit would consume significantly less IC area than two complete conventional buffers, resulting in less leakage and less yield loss.
(canceled)
A circuit for determining the characteristics of respective signals on a first pin and a second pin of a peripheral configured to be coupled to a single-conductor communications bus, including a detection circuit configured to (1) determine which signal on the first and the second pins rises fastest during a startup period, (2) output a first selected logic state indicating that the first pin is coupled to the single-conductor communications bus and the second pin is coupled to a charge storage device;
A circuit for determining the characteristics of respective signals on a first pin and a second pin of a peripheral configured to be coupled to a single-conductor communications bus and to a charge storage device, including a detection circuit configured to (1) detect, during an initial startup period, which of the first pin and the second pin is coupled to the single-conductor communications bus and which of the first pin and the second pin is coupled to the charge storage device, and (2) generate a flag signal indicating a result of the detection.
A peripheral device configured to be coupled to a single-conductor communications bus and to a charge storage device, the peripheral device including an output buffer having a first pin and a second pin, wherein either of the first pin or second pins is couplable to the single-conductor communications bus or to the charge storage device, the output buffer including:
Dependencies are inferred from the claim text.