US 2026/0221959 A1 · Circuits and Methods for Transmitting Data Over 3D Semiconductor Die Interconnects

Abstract

A circuit and method for providing matched clocks for transmitting data in bundles from a first semiconductor die to a second semiconductor die. The circuit generates a source clock from a system clock, which is distributed to a clock circuit. The clock circuit generates a bundle clock, which retimes a bundle of data lines and transmits the data to a die interconnect on the rising edge of the bundle clock. The receiving die receives the bundle clock and the received bundle data over the interconnect. The received bundle data is retimed on the rising edge of the received bundle clock. The circuit can include an enable of the bundle clock based on the transmit data within a bundle transitioning between clock cycles.

Claims21

Dependent claims

A circuit for transmitting high speed data across a multi-die, three-dimensional semiconductor device, the circuit comprising:

input data on one or more input lines containing information to be communicated from a first die to a second die over die interconnects;
one or more transmit retiming elements coupled to each of the one or more input lines to receive, retransmit, control timing of the input data and generating transmit data sent over one or more transmit lines coupled to the die interconnects;
a first clock circuit receiving a system clock signal at the first die, generating a matched source clock from the system clock, synchronizing the input data on the one or more transmit lines, the system clock signal coupled to and operable on the first clock circuit;
and
a first receiver circuit contained on the second die and coupled to the matched source clock signal from the first die and the one or more transmit lines from the first die, the matched source clock signal being matched to the received data from the one or more transmit lines from the first die and the received data synchronize by one or more receive retiming elements.

2 more elements

A circuit for providing matched clocks for transmitting data bundles from a first semiconductor die to a second semiconductor die comprising:

a first semiconductor die further comprising:
a source-clock circuit, receiving a system clock and outputting a source clock;
a bundle-clock circuit further comprising:
a bundle-clock input connected to the source clock;
a transmit-bundle clock output providing a transmit-bundle clock;
and
an interconnect transmit-bundle clock output connected to a bundle-clock die interconnect;
a data-bundle circuit comprising:
a plurality of transmit data inputs;
a data-bundle clock input receiving the transmit-bundle clock output from the bundle-clock circuit;
and
a plurality of transmit-data outputs coupled to a plurality of data-bundle die interconnects, the data-bundle circuit configured to output data on a rising edge of a transmit-bundle clock;
and
a receive-clock circuit configured to generate a receive-transmit clock, the receive clock circuit receiving the source clock and outputting the receive-transmit clock to a receive-clock die interconnect, the receive-transmit clock having substantially the same delay as the interconnect transmit-bundle clock.

11 more elements

Dependencies are inferred from the claim text.

Circuits and Methods for Transmitting Data Over 3D Semiconductor Die Interconnects

Life of this patent

Circuits and Methods for Transmitting Data Over 3D Semiconductor Die Interconnects

Life of this patent

Abstract

Claims21