Scan Clocking
AssigneeTexas Instruments Incorporated
InventorDevanathan Varadarajan
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AssigneeTexas Instruments Incorporated
InventorDevanathan Varadarajan
Estimating the term…
A method for performing a scan-based logic built-in self-test is disclosed herein. The method includes writing a first portion of a test sequence into a first subset storage elements on clock pulses of a first clock signal that is at a first clock frequency, writing the first portion of the test sequence into a second subset storage elements on clock pulses of a second clock signal that is at a second clock frequency that is greater than the first clock frequency, writing the first portion of the test sequence into a third subset of storage elements on clock pulses of a third clock signal that is at a third clock frequency that is less than the second clock frequency, and performing, after writing the first portion of the test sequence to the third subset of the plurality of storage elements, a built-in-self-test using the first portion of the test sequence.
A method, comprising:
A method, comprising:
A device, comprising:
Dependencies are inferred from the claim text.