Nand cell having large sub-threshold swing for in-memory compute
AssigneeSanDisk Technologies LLC
InventorsWei Cao, Peng Zhang, Xiang Yang
Life of this patent
Estimating the term…
Abstract
Technology for NAND memory cells having a large sub-threshold swing for in-memory compute. A NAND memory structure has alternating conductive layers and insulating layers. NAND strings extend perpendicularly through the alternating conducting layers and insulating layers. The NAND strings may be formed in memory holes that contain an insulating core, a channel, a tunnelling layer, a charge trap layer, and a blocking layer. The diameter of the insulating core and the combined thickness of the tunnelling layer, charge trap layer, and blocking layer may be sized to achieve a large sub-threshold swing in the NAND memory cells.
Claims20
An apparatus comprising:
- a memory structure having alternating conductive layers and insulating layers, the memory structure having NAND strings extending perpendicular through the alternating conductive layers and insulating layers, each NAND string having a plurality of NAND memory cell transistors, each NAND string having:
- an insulating core, the insulating core having a diameter of at least 150 nm;
- memory cell films that separate the insulating core from the conductive layers and insulating layers, the memory cell films including:
- a channel layer adjacent and surrounding the insulating core;
- a tunnelling layer adjacent and surrounding to the channel layer;
- a charge trap layer adjacent and surrounding to the tunnelling layer;
- and
- a blocking layer adjacent and surrounding to the charge trap layer, the blocking layer adjacent to the alternating conducting layers and insulating layers, wherein a combined thickness of the tunnelling layer, the charge trap layer, and the blocking layer is at least 50 nm.
A NAND memory system, comprising:
- a three dimensional NAND memory structure having alternating word line layers and insulating layers, the three dimensional NAND memory structure having NAND strings formed in memory holes that extend perpendicularly through the alternating word line layers and insulating layers, each NAND string having a plurality of NAND memory cell transistors, each memory hole comprising:
- an insulating core;
- a silicon channel adjacent and surrounding the insulating core;
- a tunnelling layer adjacent and surrounding to the silicon channel, wherein the tunnelling layer comprises a layer of SiONx;
- a charge trap layer adjacent and surrounding to the tunnelling layer, the charge trap layer comprising silicon nitride in direct contact with the SiONx of the tunnelling layer;
- and
- a blocking oxide layer adjacent and surrounding to the charge trap layer, the blocking oxide layer adjacent to the alternating word line layers and insulating layers.
A computation device, comprising:
- a three dimensional NAND memory structure having alternating conducting layers and insulating layers, the three dimensional NAND memory structure having NAND strings extending perpendicularly through the alternating conducting layers and insulating layers, each NAND string having a plurality of NAND memory cells;
- and
- one or more control circuits in communication with the three dimensional NAND memory structure, wherein the one or more control circuits are configured to:
- convert a set of numerical values to current states, wherein the current states include linear current states that correspond to linear region operation of the NAND memory cells and sub-threshold current states that correspond to sub-threshold region operation of the NAND memory cells;
- program the NAND memory cells to the current states in order to program the set of numerical values into the NAND memory cells;
- and
- perform an in-memory compute operation using the programmed NAND memory cells, wherein a sub-threshold slope of the NAND memory cells programmed to the sub-threshold current states is at least 1000 during the in-memory compute.
Dependencies are inferred from the claim text.