NOR Memory Cell with Floating Gate
AssigneeGreenliant IP LLC
InventorBing Yeh
Life of this patent
Estimating the term…
Abstract
A memory cell structure includes a mirrored pair of electrically erasable programmable nonvolatile memory cells. Each memory cell of the mirrored pair includes a word line, a source/drain region, and a portion of a shared control/erase gate. The word lines of each memory cell of the mirrored pair are electrically connected. The mirrored pair is an exactly four-node memory cell pair. The four nodes consisting of: a source node including a source/drain region of a first memory cell of the mirrored pair; a drain node including a source/drain region of a second memory cell of the mirrored pair; a word line node including the electrically connected word lines of each memory cell of the mirrored pair; and a control/erase node including the shared control/erase gate.
Claims16
A memory cell structure comprising:
- a mirrored pair of electrically erasable programmable nonvolatile memory cells,
- wherein each memory cell of the mirrored pair includes a word line, a source/drain region, and a portion of a shared control/erase gate;
- wherein the word lines of each memory cell of the mirrored pair are electrically connected;
- and
- wherein the mirrored pair is an exactly four-node memory cell pair, the four nodes consisting of:
- a source node including a source/drain region of a first memory cell of the mirrored pair;
- a drain node including a source/drain region of a second memory cell of the mirrored pair;
- a word line node including the electrically connected word lines of each memory cell of the mirrored pair;
- and
- a control/erase node including the shared control/erase gate.
A memory cell structure comprising:
- a mirrored pair of programmable nonvolatile memory cells,
- wherein each memory cell of the mirrored pair includes a word line, a source/drain region, and a portion of a shared control gate;
- wherein the word lines of each memory cell of the mirrored pair are electrically connected;
- and
- wherein the mirrored pair is an exactly four-node memory cell pair, the four nodes consisting of:
- a source node including a source/drain region of a first memory cell of the mirrored pair;
- a drain node including a source/drain region of a second memory cell of the mirrored pair;
- a word line node including the electrically connected word lines of each memory cell of the mirrored pair;
- and
- a control node including the shared control gate.
The memory cell structure of claim 8, wherein the electrically connected word lines of each memory cell of the mirrored pair are insulated from the shared control gate and offset from a portion of the shared control gate by two insulators, comprising an offset spacer and a control gate oxide.
A method of manufacturing an electrically erasable programmable nonvolatile memory cell comprising:
- after forming a base structure, including a sequence of layers on a substrate, the sequence of layers including a floating gate layer separated from the substrate by a floating gate insulation layer, a word line layer separated from the floating gate layer by a dielectric layer, and one or more protective layers over the word line layer:
- forming a trench through the sequence of layers so as to form electrically separate portions of the floating gate layer and word line layer, including a first floating gate region and first word line region for a first memory cell and a second floating gate region and second word line region for a second memory cell in a pair of memory cells, as well as first and second protective regions, positioned above the first and second word line regions, respectively, for the first and second memory cells;
- forming, in sequence, within the trench, an offset spacer, a first tunnel oxide and a second tunnel oxide, such that portions of the first floating gate region and second floating gate region closest to the trench are separated from a control gate formed in the trench by the first tunnel oxide and second tunnel oxide but not the offset spacer, and the first word line and second word line are separated from the control gate by the offset spacer, first tunnel oxide and second tunnel oxide;
- and
- forming the control gate in the trench.
Dependencies are inferred from the claim text.