Resistive random-access memory (reram) configured for overcoming the affects of read disturb

A control logic of a resistive random-access memory (ReRAM) configured to address read disturb of ReRAM cells of the ReRAM, the control logic comprising:

• a processing circuitry;
• an input/output (IO) interface communicatively connected to the processing circuit, wherein the IO interface comprises at least control signals of the ReRAM;
• and
• a memory communicatively connected to the processing circuitry, the memory containing therein instructions that when executed by the processing circuitry configure the control logic to:
• program all ReRAM cells of the ReRAM to an initial state at a first programing voltage;
• perform a clean operation on all the ReRAM cells, wherein a clean voltage is at a lower absolute value than the first programming voltage, and wherein the clean operation is performed for a predetermined period of time that is longer than a switching time of a first group of ReRAM cells that are read disturbed after a first predetermined number of reads and a second group of ReRAM cells that are read disturbed after a second predetermined number of reads, wherein the first predetermined number of reads is smaller than the second predetermined number of reads;
• and, perform a read operation on all the ReRAM cells to determine which of the ReRAM cells have been affected by a read disturb, wherein read is performed at an absolute voltage that is lower than the absolute voltage value of the clean operation.

A resistive random-access memory (ReRAM) configured to address read disturb of ReRAM cells of the ReRAM, the ReRAM comprising:

• an array of ReRAM cells;
• a word-line decoder communicatively connected to the array of ReRAM cells using at least one word-line;
• a bit-line/select-line decoder communicatively connected to the array of ReRAM cells using at least one bit-line and at least one select line;
• a control logic communicatively connected to the word-line decoder and to the bit-line/select-line decoder, the control logic comprising:
• a processing circuitry;
• an input/output (IO) interface communicatively connected to the processing circuit, wherein the IO interface comprises at least control signals of the ReRAM;
• and a memory communicatively connected to the processing circuitry, the memory containing therein instructions that when executed by the processing circuitry configure the control logic to:
• program all ReRAM cells of the ReRAM to an initial state at a first programing voltage;
• perform a clean operation on all the ReRAM cells, wherein a clean voltage is at a lower absolute value than the first programming voltage, and wherein the clean operation is performed for a predetermined period of time that is longer than a switching time of a first group of ReRAM cells that are read disturbed after a first predetermined number of reads and a second group of ReRAM cells that are read disturbed after a second predetermined number of reads, wherein the first predetermined number of reads is smaller than the second predetermined number of reads;
• and, perform a read operation on all the ReRAM cells to determine which of the ReRAM cells have been affected by a read disturb, wherein read is performed at an absolute voltage that is lower than the absolute voltage value of the clean operation.