Integrated circuit memory devices with unidirectional ports for concurrent interface operations
AssigneeRambus Inc.
InventorChristopher Haywood
Life of this patent
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Abstract
Technologies for concurrent interface operations of integrated circuit memory devices are described. An integrated circuit memory device includes an input port, a control port, and an output port. The input port receives interleaved input and a first timing reference. The interleaved input includes one or more commands or write data. The control port receives one or more control signals that specify that the interleaved input is the one or more commands or the write data. The output port transmits read data and a second timing reference. The commands or write data can be received concurrently with transmitting the read data.
Claims21
(canceled)
An integrated circuit memory device comprising:
- an input port coupled to receiver circuitry, wherein the input port is to receive interleaved input and a first timing reference, wherein the interleaved input comprises one or more commands and write data, and wherein the input port is not coupled to driver circuitry;
- a control port to receive one or more control signals that specify that the interleaved input is either the one or more commands or the write data;
- and
- an output port coupled to driver circuitry, wherein the driver circuitry is to transmit read data and a second timing reference.
A method of operating a memory device, the method comprising:
- receiving, at an input port of the memory device coupled to receiver circuitry, interleaved input and a first timing reference, wherein the interleaved input comprises one or more commands and write data, and wherein the input port is not coupled to driver circuitry;
- receiving, at a control port of the memory device, one or more control signals that specify that the interleaved input is either the one or more commands or the write data;
- and
- transmitting, via driver circuitry coupled to an output port of the memory device, read data and a second timing reference.
An integrated circuit memory device comprising:
- a first serial interface including an input port and a first control port, wherein the input port is to receive interleaved input and a first timing reference, wherein the interleaved input comprises one or more commands and write data, and wherein the first control port is to receive control signals that specify that the interleaved input is either the one or more commands or the write data;
- and
- a second serial interface including an output port and a second control port, wherein the output port is to transmit read data and a second timing reference, and wherein the second control port is to transmit an output enable signal that specifies that the output port is enabled for the read data.
Dependencies are inferred from the claim text.