Complete system power cycle detection and related methods

A method, comprising:

• detecting that a first supply voltage associated with a power-up sequence of a processor system has reached a first threshold associated with the power-up sequence of the processor system, the processor system comprising a volatile memory circuit configured to store data;
• in response to detecting that the first supply voltage has reached the first threshold, determining, during a time window of a reset event, that a second supply voltage failed to remain below a low-voltage threshold for time sufficient to result in erasure of the data, the second supply voltage supplying the volatile memory circuit;
• and
• in response to determining, during the time window of the reset event, that the second supply voltage failed to remain below the low-voltage threshold for time sufficient to result in erasure of the data, generating an indication that indicates an incomplete reset.

A boot detection circuit, comprising:

• a voltage detection circuit configured to detect that a first supply voltage associated with a power-up sequence of a processor system has reached a first threshold associated with the power-up sequence of the processor system, the processor system comprising a volatile memory circuit configured to store data;
• and
• a voltage capture circuit configured to:
• in response to detecting that the first supply voltage has reached the first threshold, determining, during a time window of a reset event, that a second supply voltage failed to remain below a low-voltage threshold for time sufficient to result in erasure of the data, the second supply voltage supplying the volatile memory circuit;
• and
• wherein the boot detection circuit is configured, in response to determining, during the time window of the reset event, that the second supply voltage failed to remain below the low-voltage threshold for time sufficient to result in erasure of the data, to generate an indication that indicates an incomplete reset.

A processor system, comprising:

• a volatile memory circuit configured to store data;
• and
• a boot detection circuit configured to:
• detect that a first supply voltage associated with a power-up sequence of the processor system has reached a boot threshold associated with the power-up sequence of the processor system;
• in response to detecting that the first supply voltage has reached the first threshold, determining, during a time window of a reset event, that a second supply voltage failed to remain below a low-voltage threshold for time sufficient to result in erasure of the data, the second supply voltage supplying the volatile memory circuit;
• and
• in response to determining, during the time window of the reset event, that the second supply voltage failed to remain below the low-voltage threshold for time sufficient to result in erasure of the data, generate an indication that indicates an incomplete reset.